MPC8323E-RDB Freescale Semiconductor, MPC8323E-RDB Datasheet - Page 69

• Manufacturer Part Number: MPC8323E-RDB
• Description: BOARD REFERENCE DESIGN
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II™ PROr
• Type: MCUr

Specifications of MPC8323E-RDB

• Contents: Reference Design Board, Software and Documentation
• Tool / Board Applications: Wired Connectivity-LIN, CAN, Ethernet, USB
• Mcu Supported Families: POWERQUICC II PRO
• Supported Devices: MPC8323E
• Rohs Compliant: Yes
• For Use With/related Products: MPC8323E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.5
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
in
Freescale Semiconductor
Table 60
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Core PLL Configuration
should be considered reserved.
VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the
core VCO frequency is in the range of 500–800 MHz.
0-1
nn
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Table 60
RCWL[COREPLL]
Core VCO frequency = core frequency × VCO divider
0000
0001
0001
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
2-5
shows the encodings for RCWL[COREPLL]. COREPLL values not listed
Table 60. e300 Core PLL Configuration
6
n
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
core_clk : csb_clk Ratio
(PLL off, csb_clk clocks
PLL bypassed
core directly)
NOTE
1.5:1
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
2.5:1
2.5:1
1:1
1:1
1:1
1:1
2:1
2:1
2:1
2:1
3:1
3:1
3:1
3:1
(PLL off, csb_clk clocks
PLL bypassed
VCO Divider
core directly)
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
÷2
÷4
÷8
÷8
Clocking
69