C8051F410-TB Silicon Laboratories Inc, C8051F410-TB Datasheet - Page 149

• Manufacturer Part Number: C8051F410-TB
• Description: BOARD PROTOTYPING W/C8051F410
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410-TB

• Contents: Board
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F410
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 18.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which will be assigned to pins P0.4 and P0.5). If a Port pin is assigned, the
Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port
pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip
Port pins that are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P1.0 and/or P1.1 for the external
oscillator, P1.2 for V
selected ADC or comparator inputs. The Crossbar skips selected pins as if they were already assigned,
and moves to the next unassigned pin. Figure 18.3 shows the Crossbar Decoder priority with no Port pins
skipped (P0SKIP, P1SKIP, P2SKIP = 0x00); Figure 18.4 shows the Crossbar Decoder priority with the
XTAL1 (P1.0) and XTAL2 (P1.1) pins skipped (P1SKIP = 0x03).
SF Signa ls
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
Figure 18.3. Crossbar Priority Decoder with No Pins Skipped
i0 i1
0
0
1
0
REF
2
0
P0SKIP[0:7]
, P0.6 for the external CNVSTR signal, P0.0 for IDA0, P0.1 for IDA1, and any
3
0
P0
4
0
5
0
cnvstr
6
0
7
0
(*4-W ire SPI Only)
x 1 x 2 vre f
0
0
1
0
Rev. 1.1
2
0
P1SKIP[0:7]
3
0
P1
4
0
5
0
6
0
7
0
C8051F410/1/2/3
0
0
1
0
2
0
P2SKIP[0:7]
3
0
P2
4
0
5
0
6
0
7
0
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