Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 5

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

PRS001003-1207
Flash Bypass Mode Register Structure
Table 2. User Mode Truth Table (Continued)
Table 3. IFREN Truth Table
To facilitate using Flash controller bypass mode for all package sizes, all the signals are
registered internally, allowing all data access to occur through a single 8-bit GPIO port
(Port A). Among the three other GPIO port pins (PortB1, PortB0, and PortC0), select one
of the input data registers or the data output register as shown in
In Flash test mode, PortA[7:0] becomes an input/output data port, and PortB[1], PortB[0],
and PortC[0] form a three input register address select as shown in
When TESTMODE pad is asserted, which is equal to 0 then:
•
•
•
•
Sector
Erase
Mass
Erase
Mode
Read
Program
Sector Erase
Mass Erase
*X stands for don’t care, and it is necessary to bias at either "H" or "L", L stands for logic Low, H
stands for logic High, and Z stands for High impedance.
PadTM[0] is shared with PortB7.
PadTM[1] is shared with PortC4.
PadTM[2] is shared with PortC5.
PadTM[3] is shared with PortC6.
H
H
H
H
L
L
IFREN=1
Read information block
Program information block
Erase information block
Erase both block
L
L
H
L
L
H
X
X
IFREN=0
Read main memory block
Program main memory block
Erase selected sector
Erase main memory block
Z
Z
Z8 Encore!
Active Active
X
Table
Table
4.
®
Active
4.
F083x Series
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Active
Active