MPC8313E-RDBB Freescale Semiconductor, MPC8313E-RDBB Datasheet - Page 43
![BOARD CPU 8313E VER 2.1](/photos/37/58/375875/mpc8313erdb_sml.jpg)
MPC8313E-RDBB
Manufacturer Part Number
MPC8313E-RDBB
Description
BOARD CPU 8313E VER 2.1
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II™ PROr
Type
MPUr
Datasheets
1.MPC8313CZQAFFB.pdf
(100 pages)
2.MPC8313E-RDBB.pdf
(52 pages)
3.MPC8313E-RDBB.pdf
(2 pages)
Specifications of MPC8313E-RDBB
Contents
Board
Processor To Be Evaluated
MPC8xxx
Data Bus Width
32 bit
Interface Type
Ethernet, USB, JTAG, SPI, UART
Dimensions
170 mm x 170 mm
Operating Supply Voltage
3.3 V
For Use With/related Products
MPC8313E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 30
It assumes the DC levels of the clock driver are compatible with the MPC8313E SerDes reference clock
input’s DC requirement.
9.2.4
The clock driver selected should provide a high quality reference clock with low-phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 40
Freescale Semiconductor
At recommended operating conditions with XV
Rising edge rate
Falling edge rate
Differential input high voltage
Differential input low voltage
Clock Driver
Single-Ended CLK
Driver Chip
describes some AC parameters for SGMII protocol.
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
AC Requirements for SerDes Reference Clocks
CLK_Out
MPC8313E PowerQUICC
Parameter
Table 40. SerDes Reference Clock Common AC Parameters
Figure 30. Single-Ended Connection (Reference Only)
33 Ω
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
DD_SRDS1
100 Ω Differential PWB Trace
™
or XV
II Pro Processor Hardware Specifications, Rev. 3
DD_SRDS2
Rise edge rate
Fall edge rate
= 1.0 V ± 5%.
Symbol
V
V
IH
IL
SD n _REF_CLK
SD n _REF_CLK
+200
Min
1.0
1.0
—
High-Speed Serial Interfaces (HSSI)
50 Ω
50 Ω
MPC8313E
–200
Max
4.0
4.0
—
SerDes Refer.
CLK Receiver
Unit
V/ns
V/ns
mV
mV
Notes
2, 3
2, 3
2
2
43
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