C8051T610DK Silicon Laboratories Inc, C8051T610DK Datasheet - Page 92
C8051T610DK
Manufacturer Part Number
C8051T610DK
Description
KIT DEV FOR C8051T61X MCU'S
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051T610DK
Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T61x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T610
For Use With
336-1507 - DAUGHTER BOARD T610 24QFN SOCKET336-1506 - DAUGHTER BOARD T610 28QFN SOCKET336-1505 - DAUGHT BOARD T610 32TQFP SOCKET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1443
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C8051T610/1/2/3/4/5/6/7
16.3. External Interrupts INT0 and INT1
The INT0 and INT1 external interrupt sources are configurable as active high or low, edge or level sensi-
tive. The IN0PL (INT0 Polarity) and IN1PL (INT1 Polarity) bits in the IT01CF register select active high or
active low; the IT0 and IT1 bits in TCON (Section “25.1. Timer 0 and Timer 1” on page 172) select level or
edge sensitive. The table below lists the possible configurations.
INT0 and INT1 are assigned to Port pins as defined in the IT01CF register (see SFR Definition 16.5). Note
that INT0 and INT0 Port pin assignments are independent of any Crossbar assignments. INT0 and INT1
will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the
Crossbar. To assign a Port pin only to INT0 and/or INT1, configure the Crossbar to skip the selected pin(s).
This is accomplished by setting the associated bit in register XBR0 (see Section “21.3. Priority Crossbar
Decoder” on page 117 for complete details on configuring the Crossbar).
IE0 (TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flags for the INT0 and INT1 external inter-
rupts, respectively. If an INT0 or INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag remains logic 1 while the input is active as defined
by the corresponding polarity bit (IN0PL or IN1PL); the flag remains logic 0 while the input is inactive. The
external interrupt source must hold the input active until the interrupt request is recognized. It must then
deactivate the interrupt request before execution of the ISR completes or another interrupt request will be
generated.
92
IT0
1
1
0
0
IN0PL
0
1
0
1
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
/INT0 Interrupt
Rev 1.0
IT1
1
1
0
0
IN1PL
1
1
0
0
Active low, edge sensitive
Active high, edge sensitive
Active low, level sensitive
Active high, level sensitive
/INT1 Interrupt
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