C8051T610DK Silicon Laboratories Inc, C8051T610DK Datasheet - Page 128
C8051T610DK
Manufacturer Part Number
C8051T610DK
Description
KIT DEV FOR C8051T61X MCU'S
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051T610DK
Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T61x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T610
For Use With
336-1507 - DAUGHTER BOARD T610 24QFN SOCKET336-1506 - DAUGHTER BOARD T610 28QFN SOCKET336-1505 - DAUGHT BOARD T610 32TQFP SOCKET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1443
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C8051T610/1/2/3/4/5/6/7
SFR Definition 21.10. P1SKIP: Port 1 Skip
SFR Address = 0xD5
SFR Definition 21.11. P2: Port 2
SFR Address = 0xA0; Bit-Addressable
128
Note: P1.6 and P1.7 are not connected to external pins on the C8051T616/7 devices. When writing code for the
Note: P2.6 and P2.7 are not connected to external pins on the C8051T616/7 devices.
Name
Reset
Name
Reset
7:0
7:0
Bit
Bit
Type
Type
Bit
Bit
C8051T616/7, P1SKIP[6:7] should be set to 11b to skip these two pins on the crossbar.
P1SKIP[7:0]
P2[7:0]
Name
Name
7
0
7
1
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
6
0
6
1
Description
5
0
5
1
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Rev 1.0
4
0
4
1
P1SKIP[7:0]
P2[7:0]
R/W
R/W
Function
Write
3
0
3
1
2
0
2
1
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
1
0
1
1
Read
0
0
0
1
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