C8051F064EK Silicon Laboratories Inc, C8051F064EK Datasheet - Page 156
C8051F064EK
Manufacturer Part Number
C8051F064EK
Description
KIT EVAL FOR C8051F064
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F064EK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F064
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F064
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1219
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- Download datasheet (2Mb)
C8051F060/1/2/3/4/5/6/7
156
Bit7:
Bit6:
Bit6:
Bit6:
Bit3:
Bit2:
Bit1:
Bit0:
EADC0
R/W
Bit7
EADC0: Enable ADC0 End of Conversion Interrupt.
This bit sets the masking of the ADC0 End of Conversion Interrupt.
0: Disable ADC0 Conversion Interrupt.
1: Enable interrupt requests generated by the ADC1 Conversion Interrupt.
CP2IE: Enable Comparator (CP2) Interrupt.
This bit sets the masking of the CP2 interrupt.
0: Disable CP2 interrupts.
1: Enable interrupt requests generated by the CP2IF flag.
CP1IE: Enable Comparator (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1IF flag.
CP0IE: Enable Comparator (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0IF flag.
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison Interrupt.
1: Enable Interrupt requests generated by ADC0 Window Comparisons.
ESMB0: Enable System Management Bus (SMBus0) Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable all SMBus interrupts.
1: Enable interrupt requests generated by the SI flag.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of SPI0 interrupt.
0: Disable all SPI0 interrupts.
1: Enable Interrupt requests generated by the SPI0 flag.
CP2IE
R/W
Bit6
CP1IE
Figure 13.21. EIE1: Extended Interrupt Enable 1
R/W
Bit5
CP0IE
R/W
Bit4
Rev. 1.2
EPCA0
R/W
Bit3
EWADC0
R/W
Bit2
ESMB0
R/W
Bit1
SFR Address:
SFR Page:
ESPI0
R/W
Bit0
0xE6
All Pages
Reset Value
00000000
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