C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 249
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
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23.
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU interven-
tion than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and five 16-bit capture/
compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the
Crossbar to Port I/O when enabled (See
page
system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source
divided by 8, Timer 0 overflow, or an external clock signal on the ECI line. Each capture/compare module may be
configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Out-
put, Frequency Output, 8-Bit PWM, or 16-Bit PWM (each is described in
controlled through the system controller's Special Function Registers. The basic PCA block diagram is shown in
Figure 23.1.
163). The counter/timer is driven by a programmable timebase that can select between six inputs as its source:
PROGRAMMABLE COUNTER ARRAY
Capture/Compare
Module 0
SYSCLK/12
Timer 0 Overflow
SYSCLK
External Clock/8
SYSCLK/4
ECI
Capture/Compare
Figure 23.1. PCA Block Diagram
Module 1
CLOCK
Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on
MUX
PCA
Crossbar
16-Bit Counter/Timer
Port I/O
Capture/Compare
Rev. 1.4
Module 2
Section
Capture/Compare
Module 3
C8051F020/1/2/3
23.2). The PCA is configured and
Capture/Compare
Module 4
249
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