C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 244

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

C8051F020/1/2/3
22.3.1. Mode 0: 16-bit Counter/Timer with Capture
In this mode, Timer 4 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the T4EX
input pin causes the following to occur:
Timer 4 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the T4 input pin as its clock
source when operating in Capture mode. Clearing the C/T4 bit (T4CON.1) selects the system clock as the input for
the timer (divided by one or twelve as specified by the Timer Clock Select bit T4M in CKCON). When C/T4 is set to
logic 1, a high-to-low transition at the T4 input pin increments the counter/timer register. As the 16-bit counter/timer
register increments and overflows from 0xFFFF to 0x0000, the TF4 timer overflow flag (T4CON.7) is set and an
interrupt will occur if the interrupt is enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RL4 (T4CON.0) and the
Timer 4 Run Control bit TR4 (T4CON.2) to logic 1. The Timer 4 External Enable EXEN4 (T4CON.3) must also be
set to logic 1 to enable a capture. If EXEN4 is cleared, transitions on T4EX will be ignored.
244
SYSCLK
1.
2.
3.
The 16-bit value in Timer 4 (TH4, TL4) is loaded into the capture registers (RCAP4H, RCAP4L).
The Timer 4 External Flag (EXF2) is set to ‘1’.
A Timer 4 interrupt is generated if enabled.
T4EX
T4
12
Crossbar
EXEN4
M
T
4
CKCON
M
0
1
T
2
M
T
1
M
T
0
Figure 22.25. T4 Mode 0 Block Diagram
0
1
TR4
Rev. 1.4
Capture
TCLK
RCAP4L
TL4
RCAP4H
TH4
CP/RL4
EXEN4
TCLK0
RCLK0
EXF4
C/T4
TR4
TF4
Interrupt