C8051F226DK Silicon Laboratories Inc, C8051F226DK Datasheet - Page 32

• Manufacturer Part Number: C8051F226DK
• Description: DEV KIT F220/221/226/230/231/236
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F226DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F22x and C8051F23x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F226
• Silicon Family Name: C8051F2xx
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F220, 221, 226, 230, 231, 236
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1241

C8051F2xx
5.
Description
The ADC subsystem for the C8051F220/1/6 consists of configurable analog multiplexer (AMUX), a pro-
grammable gain amplifier (PGA), and a 100ksps, 8-bit successive-approximation-register ADC with inte-
grated track-and-hold and programmable window detector (see Figure 5.1). The AMUX, PGA, Data
Conversion Modes, and Window Detector are all configurable under software control via the Special Func-
tion Register's shown in Figure 5.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, SFR Definition 5.3) is set to 1. The ADC sub-
system is in low power shutdown when this bit is 0.
5.1.
Any external port pin (ports 0-3) may be selected via software. The AMX0SL SFR is used to select the
desired analog input pin. (See SFR Definition 5.1). When the AMUX is enabled, the user selects which
port is to be used (bits PRTSL0-1), and then the pin in the selected port (bits PINSL0-2) to be the analog
input.
The table in
the AMUX output signal by an amount determined by the states of the AMPGN2-0 bits in the ADC Config-
uration register, ADC0CF (SFR Definition 5.2). The PGA can be software-programmed for gains of 0.5, 1,
2, 4, 8 or 16. It defaults to a gain of 1 on reset.
32
AIN31
AIN0
port pin may be configured as an
ADC (8-Bit, C8051F220/1/6 Only)
Analog Multiplexer and PGA
AIN0-31 are port 0-3
pins -- any external
analog input
??
shows AMUX functionality by channel for each possible configuration. The PGA amplifies
Figure 5.1. 8-Bit ADC Functional Block Diagram
32-to-1
AMUX
AMX0SL
X
GND
+
-
GND
VDD
ADCEN
ADC0GTH
ADC0CF
Rev. 1.6
ADC
VDD
8-Bit
SAR
ADC0CN
ADC0LTH
VDD
8
VREF
16
8
T2 OV
Comp
Dig
ADWINT