Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 29

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

UM020203-0606
D
C
B
A
-RESET
-FLASH_EN
-RD
-WR
-CS1
-RESET
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
-BHEN
-BLEN
-RD
-WR
R28 10K
R28 10K
R29
R29
0 OHm
0 OHm
25
24
23
22
21
20
19
18
48
17
16
26
28
11
12
15
47
8
7
6
5
4
3
2
1
9
25
24
23
22
21
20
19
18
48
17
14
15
28
11
26
12
13
8
7
6
5
4
3
2
1
U6
U6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CE
OE
WE
RESET
RY_BY
BYTE
AT49BV162AT
AT49BV162AT
U10
U10
TC55VCM216
TC55VCM216
C30
C30
0.1uF
0.1uF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
UBEN
LBEN
OE
WE
CE1
CE2
OP
Schematic, ZNEO™ Series MCU Development Board, Page 3 of 4
5
5
C31
C31
0.1uF
0.1uF
D15/A-1
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VCC
GND
GND
VCC
GND
GND
VPP
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
D10
D11
D12
D13
D14
C32
C32
0.1uF
0.1uF
NC
NC
NC
NC
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
VCC_33V
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
10
13
14
37
46
27
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
47
16
10
9
37
46
27
C33
C33
0.1uF
0.1uF
C34
C34
0.1uF
0.1uF
VCC_33V
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
C27
C27
0.01uF
0.01uF
C24
C24
0.01uF
0.01uF
C35
C35
0.1uF
0.1uF
-FLASH_EN
VCC_33V
C28
C28
0.01uF
0.01uF
C36
C36
0.1uF
0.1uF
C25
C25
0.01uF
0.01uF
C37
C37
0.1uF
0.1uF
VCC_33V
6
C38
C38
0.1uF
0.1uF
R30
R30
10K
10K
SN74LVC00
SN74LVC00
J7
J7
-FLASH_PR
HDR/PIN 1x2
HDR/PIN 1x2
C39
C39
0.1uF
0.1uF
PC[7:0]
1
2
C40
C40
0.1uF
0.1uF
FLASH_WRITE
4
5
4
U7B
U7B
PROTECT
4
C41
C41
0.1uF
0.1uF
ANA9
ANA8
ANA0
ANA1
ANA4
ANA5
ANA6
ANA7
ANA3
ANA2
ANA10
ANA11
-DIS_FLASH
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
3
R33
R33
10K
10K
VCC_33V
PC7_T2OUT_PWML0
VCC_33V
-MC_EN
PC6_T2IN_PWMH0
ANA[11:10]
-XM_EN
PC0_T1IN
ANA[7:0]
1
2
A[23:0]
U7A
U7A
SN74LVC00
SN74LVC00
ANA8
ANA9
-CS0
VREF
R31
R31
PC1_TOUT
PJ0_DATA8
PJ1_DATA9
PJ2_DATA10
PJ3_DATA11
-F91_WE
ANA10
ANA11
0 OHm
0 OHm
A10
A11
A12
A13
A14
A15
A20
A21
A22
A16
A18
A19
A17
A23
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
VREF
ANA11
ANA9
ANA8
FIX for REV C
ANA0
ANA1
ANA4
ANA5
ANA6
ANA7
ANA3
ANA2
ANA9
ANA8
GND
PG2_ADR10
PG3_ADR11
PG4_ADR12
PG5_ADR13
PG6_ADR14
PG7_ADR15
PH2_ANA10
PH3_ANA11
PF0_ADR0
PF1_ADR1
PF2_ADR2
PF3_ADR3
PF4_ADR4
PF5_ADR5
PF6_ADR6
PF7_ADR7
PG0_ADR8
PG1_ADR9
J6
J6
HDR/PIN 1x2
HDR/PIN 1x2
PB0_ANA0
PB1_ANA1
PB4_ANA4
PB5_ANA5
PB6_ANA6
PB7_ANA7
PB3_ANA3
PB2_ANA2
11
14
17
18
21
22
13
11
14
17
18
21
22
13
PH1_ANA9
3
4
7
8
1
3
4
7
8
1
3
3
VREF
8BIT_MDS_ENABLE
SN74CBTLV3384
SN74CBTLV3384
SN74CBTLV3384
SN74CBTLV3384
-F91_WE
PH0_ANA8
1A1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5
1OE
2OE
1A1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5
1OE
2OE
U9
U9
VCC
GND
VCC
GND
PK[7:0]
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
D[15:0]
VCC_33V
2
5
6
9
10
15
16
19
20
23
24
12
2
5
6
9
10
15
16
19
20
23
24
12
U8
U8
HDR/PIN 2x13
HDR/PIN 2x13
JP4
JP4
25
23
21
19
17
15
13
11
9
7
5
3
1
VCC_33V
GND
26
24
22
20
18
16
14
12
10
R34
R34
10K
10K
VCC_33V
8
6
4
2
PC2_nSS
PC3_SCK
PC4_MOSI
PC5_MISO
PC2_nSS
PC3_SCK
PC5_MISO
PC4_MOSI
C26
C26
0.01uF
0.01uF
C29
C29
0.01uF
0.01uF
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
PJ0
PJ1
PJ2
PJ3
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
R32
R32
PJ0_DATA8
PJ1_DATA9
PJ2_DATA10
PJ3_DATA11
PJ4_DATA12
PJ5_DATA13
PJ6_DATA14
PJ7_DATA15
PE0_DATA0
PE1_DATA1
PE2_DATA2
PE3_DATA3
PE4_DATA4
PE5_DATA5
PE6_DATA6
PE7_DATA7
-BHEN
-BLEN
-CS0
-CS1
-CS2
-CS3
-CS4
-CS5
0 OHm
0 OHm
PWMH2
PWMH1
PWML1
-RESET
DE1
TXD1
PA3
PA4
PA6
PA7
-WR
2
2
ANA_M0
ANA_M2
ANA7
ANA4
VCC_33V
PC4_MOSI
PC3_SCK
PA3_CTS0
PA4_RXD0
PA6_SCL
PA7_SDA
-FLASH_PR
-RESET
VCC_33V
VCC_33V
-BHEN
-CS4
PC1_TOUT
PD3
PD5_TXD1
PJ0
PJ1
-CS3
-CS2
A8
A13
A15
A18
A19
A2
A11
A4
A5
D1
D3
D5
D7
GND
GND
A21
A22
-CS0
D8
D10
D12
-F91_WE
A6
A10
GND
GND
D15
-WR
-BUSACK
GND
If Module is plugged onto the Dev Platform the local
RS232 interface is disabled by pin 50 of JP2
-TRSTN
-MREQ
NC
NC
NC
NC
Title
Title
Title
Size
Size
Size
Date:
Date:
Date:
B
B
B
JP1
JP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
HDR/PIN 2x30
HDR/PIN 2x30
JP2
JP2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
HDR/PIN 2x30
HDR/PIN 2x30
Z8F1285 Evaluation Module. Schematic.
Z8F1285 Evaluation Module. Schematic.
Z8F1285 Evaluation Module. Schematic.
Document Number
Document Number
Document Number
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
2
4
6
8
2
4
6
8
Monday, May 08, 2006
Monday, May 08, 2006
Monday, May 08, 2006
MEMORY AND MDS INTERFACE
-IOREQ -BLEN
-INSTRD
-BUSREQ
PC6_T2IN_PWMH0
PC7_T2OUT_PWML0
NC
NC
NC
NC
NC
NC
GND
A0
A14
A16
A3
VCC_33V
VCC_33V
GND
A1
A12
A20
-DIS_FLASH
VCC_33V
A7
A9
A17
A23
-CS1
D0
D2
D4
D6
-RD
D9
D11
D13
D14
GND
PC5_MISO
PWML2
PD6_nCTS1
PD4_RXD1
PC0_T1IN
PA5_TXD0
WAIT
ANA_M1
ANA6
ANA3
ANA5
PC2_nSS
PA2
GND
GND
PJ2
PJ3
GND
96C0999-001
96C0999-001
96C0999-001
-CS3
-CS5
PH3_ANA11
ANA_M2
ANA_M1
ANA_M0
Sheet
Sheet
Sheet
1
1
PWML2
PA2
nCTS1
RXD1
PA5
-RD
3
3
3
User Manual
-DIS_232
-DIS_IrDA
of
of
of
ANA_M[2:0]
4
4
4
Rev
Rev
Rev
C
C
C
D
C
B
A
21