AT91SAM9M10-G45-EK Atmel, AT91SAM9M10-G45-EK Datasheet - Page 59

• Manufacturer Part Number: AT91SAM9M10-G45-EK
• Description: KIT EVAL FOR AT91SAMG45/9M10
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9M10-G45-EK

• Contents: Board, Cables, Power Supply
• Processor To Be Evaluated: AT91SAM9M10
• Processor Series: AT91SAM9
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, JTAG
• Operating Supply Voltage: 5 V
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Kit Contents: Board
• Features: Two High Speed USB Hosts, LCD TFT Display
• Svhc: No SVHC (15-Dec-2010)
• Mcu Supported Families: AT91SAM9M10,
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9M10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

D
C
B
A
{4}
{4}
{4}
{4}
EBI1_FLASH_A[1..21]
EBI1_DDR_A[2..15]
EBI1_FLASH_D[0..15]
EBI1_DDR_D[0..15]
{4}
{4}
{4}
{4}
{4}
{4}
{4}
{4}
{4}
BA0_EBI1
BA1_EBI1
CKE_EBI1
CLK_EBI1
NCLK_EBI1
CS_EBI1
CAS_EBI1
RAS_EBI1
W E_EBI1
IMPORTANT note about system booting:
The bootROM allows booting from the block 0 of a NandFlash connected
on CS3. However, the bootROM does not feature ECC (Error Checking and
Correction) on NandFlash.
Most of the NandFlash vendors do not guarantee anymore that block 0
is error free. Therefore we advise the bootstrap program to be located
into another device supported by the bootrom (DataFlash, Serial Flash,
SDCARD or EEPROM) and implement NandFlash access with ECC.
8
8
BA0_EBI1
BA1_EBI1
CKE_EBI1
CLK_EBI1
NCLK_EBI1
CS_EBI1
CAS_EBI1
RAS_EBI1
W E_EBI1
EBI1_DDR_A2
EBI1_DDR_A3
EBI1_DDR_A4
EBI1_DDR_A5
EBI1_DDR_A6
EBI1_DDR_A7
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A10
EBI1_DDR_A11
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_DDR_A14
EBI1_DDR_A15
(NCS1)
(SDA10)
G2
G3
G8
G7
G1
H8
H3
H7
K2
K8
K3
H2
K7
F9
F2
E8
F8
F7
F3
J2
J8
J3
J7
L2
L8
L3
L7
{4}
MN8
MN8
MT47H64M8CF-3 -F
MT47H64M8CF-3 -F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
ODT
CKE
CK
CK
CS
CAS
RAS
WE
RFU1
RFU2
RFU3
7
7
EBI1_NAND_FSH_D[0..15]
DDR2 SDRAM
DDR2 SDRAM
{3}
{3}
EBI1_NANDOE
EBI1_NANDW E
RDQS/DM
RDQS/NU
{3,4}
VSSDL
{3}
{3}
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VDDL
VREF
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DQS
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
{3}
PC5
PC4
PC14
PC8
C8
C2
D7
D3
D1
D9
B1
B9
B7
A8
B3
A2
A1
E9
H9
L1
E1
A9
C1
C3
C7
C9
E2
A3
E3
J1
K9
A7
B2
B8
D2
D8
E7
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D3
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
1V8
VREF1
C92
C92
C94
C94
C96
C96
C98
C98
C100
C100
C102
C102
C104
C104
C106
C106
C108
C108
C111
C111
(NANDCLE)
(NANDALE)
(NCS3)
(RDY/BSY)
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
C116
C116
100n
100n
6
6
DQS0_EBI1 {4}
DQM0_EBI1 {4}
1
JP10
JP10
SIP2
SIP2
2
1V8
1V8
R59
R59
R62
R62
R57
R57
R58
R58
R60
R60
R61
R61
EBI1_DDR_A2
EBI1_DDR_A3
EBI1_DDR_A4
EBI1_DDR_A5
EBI1_DDR_A6
EBI1_DDR_A7
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A10
EBI1_DDR_A11
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_DDR_A14
EBI1_DDR_A15
0R
0R
0R
0R
470k
470k
0R
0R
1k
1k
470k
470k
BA0_EBI1
BA1_EBI1
CKE_EBI1
CLK_EBI1
NCLK_EBI1
CS_EBI1
CAS_EBI1
RAS_EBI1
W E_EBI1
5
5
(SDA10)
R63
R63
0R
0R
DNP
DNP
RE
W E
CE
RB
W P
A10
B10
G2
G3
G8
G7
G1
G5
G3
G8
H8
H3
H7
K2
K8
K3
H2
K7
L2
L8
F9
F2
E8
F8
F7
F3
L3
L7
D5
C4
D4
C7
C6
C8
C3
A1
A2
A9
B1
B9
D6
D7
D8
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F8
L1
L2
J2
J8
J3
J7
MN9
MN9
MT47H64M8CF-3 -F
MT47H64M8CF-3 -F
MN11
MN11
MT29F2G08ABDHC:D
MT29F2G08ABDHC:D
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
ODT
CKE
CK
CK
CS
CAS
RAS
WE
RFU1
RFU2
RFU3
CLE
ALE
RE
WE
CE
R/B
WP
LOCK
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
N.C15
N.C16
N.C17
N.C18
N.C19
N.C20
N.C21
N.C22
N.C23
N.C24
N.C25
DDR2 SDRAM
DDR2 SDRAM
NAND FLASH
NAND FLASH
RDQS/DM
RDQS/NU
VSSDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
N.C26
N.C27
N.C28
N.C29
N.C30
N.C31
N.C32
N.C33
N.C34
N.C35
N.C36
N.C37
N.C38
N.C39
VDDL
VREF
DQS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
C8
C2
D7
D3
D1
D9
B1
B9
B7
A8
B3
A2
A1
E9
H9
L1
E1
A9
C1
C3
C7
C9
E2
A3
E3
J1
K9
A7
B2
B8
D2
D8
E7
H4
J4
K4
K5
K6
J7
K7
J8
H3
J3
H5
J5
H6
G6
H7
G7
L9
L10
M1
M2
M9
M10
D3
G4
H8
J6
C5
F7
K3
K8
4
4
1V8
VREF1
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_DDR_D14
EBI1_DDR_D15
1V8
C117
C117
100n
100n
C93 100n
C93 100n
C95 100n
C95 100n
C97 100n
C97 100n
C99 100n
C99 100n
C101 100n
C101 100n
C103 100n
C103 100n
C105 100n
C105 100n
C107 100n
C107 100n
C109 100n
C109 100n
C112 100n
C112 100n
DQS1_EBI1 {4}
DQM1_EBI1 {4}
C118 100n
C118 100n
C119 100n
C119 100n
C120 100n
C120 100n
C121 100n
C121 100n
{3,5}
{3}
{3}
EBI1_NW E/NW R0/CFW E
EBI1_NCS0
DDR_VREF
3
3
{3}
EBI1_NRD/CFOE
1V8
VREF1
1
JP9
JP9
2
R200
R200
R53
R53
R54
R54
R55
R55
AT91SAM9M10-G45-EK
AT91SAM9M10-G45-EK
AT91SAM9M10-G45-EK
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
EBI1_MEMORY
EBI1_MEMORY
EBI1_MEMORY
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
R56
R56
470k
470k
1V8
0R
0R
100k
100k
0R
0R
100k
100k
2
2
E8
D8
C8
B8
A8
B7
A7
C7
A2
B2
C2
A1
B1
C1
D2
D1
D4
B6
A6
C6
B3
C3
B4
B5
C4
D6
E7
F8
C5
A5
MN10
MN10
M58W R032KT_VFBGA56
M58W R032KT_VFBGA56
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
NC/A21
CLK
RESET
LATCH
WP
CE
OE
WE
VPP
REV
REV
REV
SCALE
SCALE
SCALE
A2
A2
A2
A
A
A
DNP
DNP
MODIF.
MODIF.
MODIF.
1/1
1/1
1/1
VDDQ
VDDQ
VSSQ
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
WAIT
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VSS
VSS
Derek
Derek
Derek
NC
PP
PP
PP
DES.
DES.
DES.
F7
E6
E5
G5
E4
G3
E3
G1
G7
F6
F5
F4
D5
F3
F2
E2
D3
D7
A4
G4
E1
G6
A3
F1
G2
G8
08-apr-10
08-apr-10
08-apr-10
05-Feb-10
05-Feb-10
05-Feb-10
DATE
DATE
DATE
1V8
1
1
C110
C110
C113
C113
C114
C114
C115
C115
EBI1_FLASH_D0
EBI1_FLASH_D1
EBI1_FLASH_D2
EBI1_FLASH_D3
EBI1_FLASH_D4
EBI1_FLASH_D5
EBI1_FLASH_D6
EBI1_FLASH_D7
EBI1_FLASH_D8
EBI1_FLASH_D9
EBI1_FLASH_D10
EBI1_FLASH_D11
EBI1_FLASH_D12
EBI1_FLASH_D13
EBI1_FLASH_D14
EBI1_FLASH_D15
PP
PP
PP
VER.
VER.
VER.
REV.
REV.
REV.
A2
A2
A2
100n
100n
100n
100n
100n
100n
100n
100n
11-FEB-10
11-FEB-10
11-FEB-10
SHEET
SHEET
SHEET
DATE
DATE
DATE
6
6
6
12
12
12
D
C
B
A