ATF15XX-DK3 Atmel, ATF15XX-DK3 Datasheet - Page 41

• Manufacturer Part Number: ATF15XX-DK3
• Description: KIT DEV FOR ATF15XX CPLD'S
• Manufacturer: Atmel
• Series: Logic Doubling®r
• Type: CPLDr

Specifications of ATF15XX-DK3

• Contents: CPLD Programmer Board, 44-TQFP, Socket Adapter Board, Download Cable, CD-ROMs. Samples and User Guide
• Processor To Be Evaluated: ATF15xx
• Interface Type: JTAG
• Operating Supply Voltage: 1.8 V, 3.3 V, 5 V
• For Use With/related Products: ATF15xx Family of CPLD
• For Use With: ATF15XXDK3-SAJ84 - ADAPTER SKT ATF15XXBE 84/84PLCCATF15XXDK3-SAA100 - ADAPTER SKT ATF15XXB PLCC/TQFPATF15XXDK3-SAJ44 - ADAPTER SKT ATF15XXBE 84/44PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ATF15xx-DK3 Development Kit User Guide
------------------------------------------------------------------------------------
-- Library Declaration
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all;
------------------------------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------------------------------
entity f02_44TQFP is
------------------------------------------------------------------------------------
-- Pin Assignment
------------------------------------------------------------------------------------
end entity f02_44TQFP;
------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------
architecture LOGIC of f02_44TQFP is
------------------------------------------------------------------------------------
-- Internal Signal Declaration
------------------------------------------------------------------------------------
port
(
);
attribute pinnum: string;
attribute pinnum of GCLK1: signal is"37";
attribute pinnum of GCLK2: signal is"40";
attribute pinnum of GCLR: signal is"39";
attribute pinnum of SW: signal is"12,13,14,15";
attribute pinnum of DSP1: signal is"23,18,21,30,33,27";
attribute pinnum of DSP4: signal is"42,35,43,6,10,3";
attribute pinnum of LED: signal is"19,22,25,28";
signal CNT1: unsigned(15 downto 0);
signal iCLK : std_logic;
GCLK1
GCLK2
GCLR
SW
DSP1
DSP4
LED
: in std_logic;
: in std_logic;
: in std_logic;
: inout std_logic_vector(5 downto 0);-- 7-segment display LEDs (F to A)
: inout std_logic_vector(5 downto 0);-- 7-segment display LEDs (F to A)
: out std_logic_vector(4 downto 1)-- LEDs
: in std_logic_vector(8 downto 5);-- Switches
-- 2MHz clock (positive edge)
-- 2MHz clock (negative edge)
-- Register reset
Schematic Diagrams and VHDL File
3605B–PLD–05/06
4-7