HW-SD1800A-DSP-SB-UNI-G Xilinx Inc, HW-SD1800A-DSP-SB-UNI-G Datasheet - Page 17

• Manufacturer Part Number: HW-SD1800A-DSP-SB-UNI-G
• Description: KIT DEVELOPMENT SPARTAN 3ADSP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A DSPr
• Type: DSPr

Specifications of HW-SD1800A-DSP-SB-UNI-G

• Contents: Development Platform, Power Supply and software
• Silicon Manufacturer: Xilinx
• Features: 10/100/1000 PHY, JTAG Programming And Configuration Port
• Silicon Family Name: Spartan-3A
• Silicon Core Number: 3SD1800A-FG676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Spartan 3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1574; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-DB-UNI-G; HW-SD1800A-DSP-SB-UNI-G

Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
R
Table 7: Ethernet PHY Interface Signals
The PHY address is set to 0b00001 by default. PHY address 0b00000 is reserved for a test
mode and should not be used. Three-pad resistor jumpers are used to set the strapping
options. These jumper pads provide the user with the ability to change the settings by
moving the resistors. The dual-function pins that are used for both a strapping option and
to drive an LED have a set of two jumpers per pin. The dual-function pins are indicated by
an asterisk in the table.
The default options as indicated in
mode, Speed advertised as 10/100/1000 Mb/s, PHY address 0b00001, IEEE Compliant
and Non-compliant support, straight cable in non-MDIX mode, auto-MDIX mode enabled,
Single node (NIC) and CLK_TO_MAC enabled. These and other settings are enabled by
three-pad jumpers with a resistor connecting either pads 1 and 2 or pads 2 and 3.
Ethernet PHY Signal
ETH_GTX_CLK
ETH_Tx_EN
ETH_Tx_ER
ETH_MDIO
ETH_Tx_D
ETH_Tx_D
ETH_Tx_D
ETH_Tx_D
ETH_Tx_D
ETH_Tx_D
ETH_Tx_D
ETH_Tx_D
ETH_MDC
ETH_RST#
ETH_CRS
www.xilinx.com
FPGA Pin
H7
G6
K9
K8
D3
G4
G1
B2
B1
E4
E3
F4
F5
J8
J9
Table 8
are Auto-Negotiation enabled, Full Duplex
Ethernet PHY Signal
ETH_Rx_CLK
ETH_Tx_CLK
ETH_Rx_DV
ETH_Rx_ER
ETH_MCLK
ETH_Rx_D0
ETH_Rx_D1
ETH_Rx_D2
ETH_Rx_D3
ETH_Rx_D4
ETH_Rx_D5
ETH_Rx_D6
ETH_Rx_D7
ETH_INT#
ETH_COL
Functional Description
FPGA Pin
Ab3
Ab4
Aa4
D1
N6
D2
Y3
C2
G2
G5
Y4
P1
P2
J1
J3
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