AT91SAM9G20-EK Atmel, AT91SAM9G20-EK Datasheet - Page 13

• Manufacturer Part Number: AT91SAM9G20-EK
• Description: KIT EVAL FOR AT91SAM9G20 MCU
• Manufacturer: Atmel
• Type: MCUr

Specifications of AT91SAM9G20-EK

• Contents: Board, Cables, CD, Power Supply
• Processor To Be Evaluated: AT91SAM9G20
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB
• Core: RISC
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Silicon Core Number: AT91SAM9G20
• Silicon Family Name: ARM
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9G20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.1
AT91SAM9G20-EK Evaluation Board User Guide
AT91SAM9G20 Microcontroller
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Incorporates the ARM926EJ-S
Additional Embedded Memories
External Bus Interface (EBI)
USB 2.0 Full Speed (12 Mbits per second) Device Port
USB 2.0 Full Speed (12 Mbits per second) Host and Double Port
Ethernet MAC 10/100 Base T
Image Sensor Interface
Bus Matrix
Fully-featured System Controller, including
Reset Controller (RSTC)
Clock Generator (CKGR)
– DSP Instruction Extensions, ARM Jazelle
– 32-KByte Data Cache, 32-KByte Instruction Cache, Write Buffer
– CPU Frequency 400 MHz
– Memory Management Unit
– EmbeddedICE
– One 64-KByte Internal ROM, Single-cycle Access at Maximum Matrix Speed
– Two 16-KByte Internal SRAM, Single-cycle Access at Maximum Matrix Speed
– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash
– On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
– Media Independent Interface or Reduced Media Independent Interface
– 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
– Six 32-bit-layer Matrix
– Boot Mode Select Option, Remap Command
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control
– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup
– 3 to 20 MHz On-chip Oscillator, One up to 800 MHz PLL and One up to 100 MHz PLL
Power Supply, Providing a Permanent Slow Clock
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, Debug Communication Channel Support
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ARM
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Thumb
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Technology for Java
Processor
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Board Description
Acceleration
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6413C–ATARM–18-Feb-09
Section 3
3-1