STEVAL-IFS003V1 STMicroelectronics, STEVAL-IFS003V1 Datasheet - Page 27
![BOARD STLM75/STDS75/ST72F651](/photos/9/18/91877/steval-ifs003v1_sml.jpg)
STEVAL-IFS003V1
Manufacturer Part Number
STEVAL-IFS003V1
Description
BOARD STLM75/STDS75/ST72F651
Manufacturer
STMicroelectronics
Datasheets
1.STLM75DS2F.pdf
(40 pages)
2.STDS75M2F.pdf
(39 pages)
3.STEVAL-IFS003V1.pdf
(161 pages)
4.STEVAL-IFS003V1.pdf
(4 pages)
Specifications of STEVAL-IFS003V1
Design Resources
STEVAL-IFS003V1 Gerber Files STEVAL-IFS003V1 Schematic STEVAL-IFS003V1 Bill of Materials
Sensor Type
Temperature
Sensing Range
-55°C ~ 125°C
Interface
I²C
Voltage - Supply
7.5 V ~ 19 V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST72F651, STDS75, STLM75
Silicon Manufacturer
ST Micro
Silicon Core Number
STLM75/STDS75 And ST72F651AR6
Kit Application Type
Sensing - Temperature
Application Sub Type
Temperature Sensor
Kit Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Sensitivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-6238
- STLM75DS2F PDF datasheet
- STDS75M2F PDF datasheet #2
- STEVAL-IFS003V1 PDF datasheet #3
- STEVAL-IFS003V1 PDF datasheet #4
- Current page: 27 of 161
- Download datasheet (3Mb)
6.2 RESET SEQUENCE MANAGER (RSM)
6.2.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
Figure 17. RESET Sequences
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
V
V
IT+(LVD)
IT-(LVD)
RUN
V
DD
ACTIVE PHASE
Figure
RESET
LVD
6.2.2:
t
t
w(RSTL)out
h(RSTL)in
RUN
Doc ID 7215 Rev 4
ACTIVE
PHASE
SHORT EXT.
RESET
DELAY
The basic RESET sequence consists of 3 phases
as shown in
■
■
■
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behaviour.
t
Active Phase depending on the RESET source
Min 512 CPU clock cycle delay (see
and
RESET vector fetch
h(RSTL)in
t
w(RSTL)out
RUN
Figure 20
WATCHDOG UNDERFLOW
Figure
ACTIVE
PHASE
LONG EXT.
RESET
17:
INTERNAL RESET (min 512 T
VECTOR FETCH
RUN
ACTIVE
PHASE
WATCHDOG
ST72651AR6
RESET
t
w(RSTL)out
Figure 19
RUN
27/161
CPU
)
1
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