DK86065-2 Fujitsu Semiconductor America Inc, DK86065-2 Datasheet - Page 9

KIT EVAL 16BIT DAC FOR MB86065

DK86065-2

Manufacturer Part Number
DK86065-2
Description
KIT EVAL 16BIT DAC FOR MB86065
Manufacturer
Fujitsu Semiconductor America Inc
Datasheets

Specifications of DK86065-2

Number Of Dac's
1
Number Of Bits
14
Outputs And Type
1, Differential
Sampling Rate (per Second)
1G
Data Interface
Serial
Dac Type
Current
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
MB86065
For Use With
865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
865-1011
September 2007 Version 1.01
FME/MS/DAC80S/DS/5344
MB86065 14-bit 1+GSa/s DAC
1.1.5 Loop Clock
Maintaining valid clock-to-data timing becomes increasingly difficult at higher clock rates, particularly
over tolerance with device-to-device variations. The MB86065 minimises potential problems through
its DDR data interface and by providing a unique loop-clock facility.
The on-chip ‘loop’ consists of an LVDS input buffer connected to an LVDS output buffer through a
programmable delay stage. This loop-through, and the associated tracking from/to the data
generating device, can be incorporated in the feedback loop of a Delay-Locked Loop (DLL) or Phase-
Locked Loop (PLL) clock generator, within the generating device. This enables the system to
compensate for variations in input/output (I/O) and propagation delays in both the data generating
device and the DAC. PCB and/or cable propagation delays within the loop are also compensated for
but these are not expected to exhibit significant variation between systems. It is the I/O & on-chip
delays that will dominate.
With the loop clock implemented as illustrated in Figure 3, increasing the Clock Output delay delays
the data arriving at the DAC relative to the DAC input clock. By contrast increasing the Loop Clock
delay, within the feedback loop of the DLL/PLL, advances the relative timing.
Copyright © 2004-2007 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
FPGA
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
It is important to make sure that the Clock Output frequency is within the specification of
the DLL/PLL. If it is too high an appropriate divided clock output should be programmed as
detailed in Table 5.
Reference
Clock
Feedback
Clock
DLL/
PLL
Clock x2 (1GHz)
Clock ÷2
(500MHz)
Figure 3 Loop Clock Implementation
Fujitsu MB86064 DAC
Increase delay to
‘retard’ data
Production
Increase delay to
‘advance’ data
(500 MHz)
Clock
DAC
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