ISL6310EVAL1Z Intersil, ISL6310EVAL1Z Datasheet - Page 23

• Manufacturer Part Number: ISL6310EVAL1Z
• Description: EVALUATION BOARD FOR ISL6310
• Manufacturer: Intersil

Specifications of ISL6310EVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.5V
• Current - Output: 60A
• Voltage - Input: 5 ~ 12V
• Regulator Topology: Buck
• Frequency - Switching: 400kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6310
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the per-channel switching frequency, F
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔV
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
FIGURE 23. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
0
LOG
20
log
⎛
⎝
R2
------- -
R1
⎞
⎠
F
Z1
F
F
LC
Z2
F
F
23
CE
P1
F
0
F
20
P2
log
SW
G
CL
COMPENSATION GAIN
d
---------------------------------
OPEN LOOP E/A GAIN
.
CLOSED LOOP GAIN
MAX V
G
V
MOD
MODULATOR GAIN
OSC
FREQUENCY
⋅
IN
MAX
G
FB
.
ISL6310
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
page 9 and Equation 2), a voltage develops across the bulk
capacitor ESR equal to I
capacitors are selected, the maximum allowable ripple
voltage, V
inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV
Equation 41 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 42
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
ΔV
L
L
L
≤
≤
≥
MAX
≈
2 N C V
---------------------------------
(
--------------------------------- -
(
1.25
(
ESR
⋅
ESL
(
(
. This places an upper limit on inductance.
ΔI
ΔI
⋅
) N C
)
⋅
PP(MAX)
)
)
)
2
2
⎛
⎝
------------------------------------------------------------------- -
⋅
⋅
V
F
di
---- -
dt
⋅
IN
O
SW
+
⋅
⋅
MAX
–
(
N V
⋅
ESR
ΔV
ΔV
V
, determines the lower limit on the
⋅
IN
.
MAX
MAX
OUT
) ΔI
⋅
V
⋅
C,PP
PP MAX
–
–
⎞ V
⎠
(
(
(
ΔI ESR
⋅
ΔI ESR
(ESR). Thus, once the output
⋅
⋅
OUT
)
)
)
⋅
⎛
⎝
V
IN
–
V
O
⎞
⎠
August 7, 2008
(EQ. 41)
(EQ. 42)
(EQ. 39)
(EQ. 40)
FN9209.4