ISL6310EVAL1Z Intersil, ISL6310EVAL1Z Datasheet - Page 15

• Manufacturer Part Number: ISL6310EVAL1Z
• Description: EVALUATION BOARD FOR ISL6310
• Manufacturer: Intersil

Specifications of ISL6310EVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.5V
• Current - Output: 60A
• Voltage - Input: 5 ~ 12V
• Regulator Topology: Buck
• Frequency - Switching: 400kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6310
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

Soft-Start
During soft-start, the DAC voltage ramps linearly from zero
to the programmed level. The PWM signals remain in the
high-impedance state until the controller detects that the
ramping DAC level has reached the output-voltage level.
This protects the system against the large, negative inductor
currents that would otherwise occur when starting with a
pre-existing charge on the output as the controller attempted
to regulate to zero volts at the beginning of the soft-start
cycle. The Output soft-start time, t
period equal to 64 switching cycles after the ENLL has
exceeded its POR level, followed by a linear ramp with a rate
determined by the switching period, 1/F
For example, a regulator with 450kHz switching frequency
having REF voltage set to 1.2V has t
t
SS
2. The voltage on ENLL must be above 0.66V. The EN input
3. The driver bias voltage applied at the PVCC pins must
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6310 in shutdown until the voltage at ENLL
rises above 0.66V. The enable comparator has 100mV of
hysteresis to prevent bounce.
reach the internal power-on reset (POR) rising threshold.
In order for the ISL6310 to begin operation, PVCC is the
only pin that is required to have a voltage applied that
exceeds POR. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6310 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 5)
When each of these conditions is true, the controller
immediately begins the soft-start sequence.
=
64
------------------------------------------- -
CIRCUIT
FAULT LOGIC
SOFT-START
POR
+
DAC
AND
ISL6310 INTERNAL CIRCUIT
F
SENSITIVE ENABLE (ENLL) FUNCTION
SW
⋅
1280
ENABLE
COMPARATOR
15
+
-
0.66V
SS
, begins with a delay
SS
EXTERNAL CIRCUIT
VCC
PVCC
ENLL
SW
equal to 3.55ms.
.
10.7kΩ
1.40kΩ
+12V
(EQ. 12)
ISL6310
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft-start and ramps to zero during the first 640
cycles of soft-start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative
bias.
During the first 640 cycles of soft-start (704 cycles following
enable) the DAC voltage increments the reference in 25mV
steps. The remainder of soft-start sees the DAC ramping
with 12.5mV steps.
The ISL6310 also has the ability to start up into a
pre-charged output as shown in Figure 12, without causing
any unnecessary disturbance. The FB pin is monitored
during soft-start, and should it be higher than the equivalent
internal ramping reference voltage, the output drives hold
both MOSFETs off. Once the internal ramping reference
exceeds the FB pin potential, the output drives are enabled,
allowing the output to ramp from the pre-charged level to the
final level dictated by the reference setting. Should the
output be pre-charged to a level exceeding the reference
setting, the output drives are enabled at the end of the
soft-start period, leading to an abrupt correction in the output
voltage down to the “reference set” level.
Fault Monitoring and Protection
The ISL6310 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to the sensitive load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 13
outlines the interaction between the fault monitors and the
power good signal.
FIGURE 12. SOFT-START WAVEFORMS FOR ISL6310-BASED
GND>
GND>
OUTPUT PRECHARGED
BELOW DAC LEVEL
OUTPUT PRECHARGED
MULTI-PHASE CONVERTER
ABOVE DAC LEVEL
T1
T2
T3
V
OUT
ENLL (5V/DIV)
(0.5V/DIV)
August 7, 2008
FN9209.4