ISL6310 INTERSIL [Intersil Corporation], ISL6310 Datasheet

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... An optional droop function is also implemented and can be disabled for applications having less stringent output voltage variation requirements or experiencing less severe step loads. A unique feature of the ISL6310 is the combined use of both DCR and r current sensing. Load line voltage DS(ON) positioning and overcurrent protection are accomplished ...

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... Pinout OFST COMP VDIFF RGND VSEN 2 ISL6310 ISL6310 (32 LD QFN) TOP VIEW REF 1 2 VCC GND BOOT1 23 PHASE1 22 OVP 21 REF1 20 ENLL 19 PHASE2 18 BOOT2 17 UGATE2 16 FN9209.3 December 12, 2006 ...

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... ISUM IREF RGND VSEN x1 x1 VDIFF UVP OVP OVP +150mV x 0.82 REF1 DAC REF0 DAC REF E/A FB COMP OFST OFFSET 3 ISL6310 OCSET PGOOD OVP 100µA OC +1V SOFT-START AND FAULT LOGIC 0.2V CLOCK AND SAWTOOTH GENERATOR ∑ PWM1 ∑ PWM2 CHANNEL 1 CURRENT N BALANCE ∑ ...

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... Typical Application - ISL6310 FB VDIFF VSEN RGND +5V 2PH VCC OFST FS DAC ISL6310 REF REF1 REF0 OVP PGOOD +12V GND ENLL IREF DROOP ICOMP OCSET 4 ISL6310 +12V COMP PVCC BOOT1 UGATE1 PHASE1 ISEN1 LGATE1 +12V BOOT2 UGATE2 PHASE2 ISEN2 LGATE2 ISUM LOAD FN9209.3 ...

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... VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . +5V to 12V ±5% Ambient Temperature (ISL6310CR, ISL6310CRZ 0°C to +70°C Ambient Temperature (ISL6310IR, ISL6310IRZ .-40°C to +85°C CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied ...

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... Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance OVER TEMPERATURE SHUTDOWN Thermal Shutdown Setpoint (Note 3) Thermal Recovery Setpoint (Note 3) NOTE: 3. Parameter magnitude guaranteed by design. Not 100% tested. 6 ISL6310 TEST CONDITIONS R = 10k to ground 100pF 10k to ground 100pF, Load = ± ...

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... Tying the 2PH pin to GND causes the controller to operate in a single phase mode. REF0 and REF1 (Pins 30, 21) These pins make up the 2-Bit input that selects the fixed DAC reference voltage. These pins respond to TTL logic thresholds. The ISL6310 decodes these inputs to establish t FUGATE t RLGATE ...

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... The DAC pin is the direct output of the internal DAC. This pin Ω is connected to REF pin using left open if an external reference is used. 8 ISL6310 REF (Pin 1) The REF input pin is the positive input of the error amplifier. This pin can be connected to the DAC pin using a resistor Ω ...

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... ISL6310 controller. Interleaving The switching of each channel in an ISL6310-based converter is timed to be symmetrically out of phase with the other channel result, the two-phase converter has a combined ripple frequency twice the frequency of one of its phases ...

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... MOSFET and turn on the channel 1 synchronous MOSFET. In the default channel configuration, the PWM2 pulse terminates 1 cycle after the PWM1 pulse. One switching cycle for the ISL6310 is defined as the time between consecutive PWM pulse terminations (turn-off of the upper MOSFET on a channel). Each cycle begins when a switching clock signal commands the upper MOSFET to go off. The other channel’ ...

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... The ISL6310 senses the channel load current by sampling the voltage across the lower MOSFET simply Figure 5. A ground-referenced operational amplifier, internal SEN to the ISL6310, is connected to the PHASE node through a , after the resistor the voltage drop across the r while it is conducting. The resulting current into the ISEN pin is proportional to the channel current, I sampled and held as described in the See “ ...

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... This dependence of output voltage on load current is often termed “droop” or “load line” regulation. VID DAC The Droop is an optional feature in the ISL6310. It can be enabled by connecting ICOMP pin to DROOP pin as shown in Figure 6. To disable it, connect the DROOP pin to IREF + pin ...

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... R to compensate for the rise in DCR due to COMP temperature. Output Voltage Offset Programming The ISL6310 allows the designer to accurately adjust the offset voltage by connecting a resistor, R pin to VCC or GND. When R is connected between OFS OFS and VCC, the voltage across it is regulated to 1.5V. This ...

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... Enable and Disable While in shutdown mode, the PWM outputs are held in a high-impedance state to assure the drivers remain off. The following input conditions must be met before the ISL6310 is released from shutdown mode. 1. The bias voltage applied at VCC must reach the internal power-on reset (POR) rising threshold ...

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... The remainder of soft-start sees the DAC ramping 1.40kΩ with 12.5mV steps. The ISL6310 also has the ability to start up into a pre- charged output as shown in Figure 12, without causing any unnecessary disturbance. The FB pin is monitored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both MOSFETs off ...

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... OCSET its trip point if it was the fixed voltage, V Actions are taken by the ISL6310 to protect the load when an overvoltage condition occurs, until the output voltage falls back within set limits. 100µA At the inception of an overvoltage event, all LGATE signals are commanded high, and the PGOOD signal is driven low ...

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... Principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circuitry, and 17 ISL6310 the maximum amount of load current. Generally speaking, , the most economical solutions are those in which each OCSET phase handles between 25 and 30A ...

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... See “Layout Considerations” on page 24. paragraph for thermal transfer improvement suggestions. 18 ISL6310 When designing the ISL6310 into an application recommended that the following calculation is used to ensure safe operation at the desired frequency for the selected MOSFETs. The total gate drive power losses, ...

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... Q2 Load Line Regulation Component Selection (DCR S Current Sensing) For accurate load line regulation, the ISL6310 senses the total output current by detecting the voltage across the output inductor DCR of each channel (As described in the Load Line Regulation section). As Figure 18 illustrates, an R-C network is required to accurately sense the inductor DCR voltage and convert this information into a “ ...

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... Treating the system as though it were a voltage-mode regulator, by compensating the L-C poles and the ESR zero of the voltage mode approximation, ΔV ΔV 1 ΔI and (OPTIONAL COMP VDIFF LOAD-LINE REGULATED ISL6310 CIRCUIT 2 V OUT I TRAN ISL6310 FN9209.3 December 12, 2006 ...

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... Figure 22 highlights the voltage-mode control loop for a synchronous-rectified buck converter, applicable, with a small number of adjustments, to the multi-phase ISL6310 circuit. The output voltage (V ⋅ L reference voltage, VREF, level. The error amplifier output ESR (COMP pin voltage) is compared with the oscillator (OSC) ⋅ ...

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... ISL6310 EXTERNAL CIRCUIT FIGURE 22. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN The compensation network consists of the error amplifier (internal to the ISL6310) and the external R components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F ; typically 0 ...

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... ESR, and ESL (equivalent series inductance). At the beginning of the load transient, the output capacitors supply all of the transient current. The output voltage will 23 ISL6310 initially deviate by an amount approximated by the voltage drop across the ESL. As the load current increases, the (in voltage drop across the ESR increases linearly until the load FB current reaches its final value ...

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... Low ESL, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and 24 ISL6310 falling edge voltage spikes. The spikes result from the high current slew rate produced by the upper MOSFET turn on and off. Place them as close as possible to each upper MOSFET drain to minimize board parasitics and maximize suppression ...

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... EMI pick-up also important to place current sense components close to their respective pins on the ISL6310, including the RISEN resistors, RS, RCOMP, CCOMP. For proper current sharing route two separate symmetrical as possible traces from the corresponding phase node for each RISEN ...

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... REF0 OVP PGOOD +12V GND ENLL IREF DROOP OCSET ICOMP ISUM R COMP R OCSET C COMP FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS 26 ISL6310 LOCATE CLOSE TO IC (MINIMIZE CONNECTION PATH) +12V C HF01 COMP PVCC C HF1 BOOT1 C BOOT1 UGATE1 PHASE1 ISEN1 R ISEN1 LGATE1 ...

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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 27 ISL6310 L32.5x5 32LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C) ...