NCP1012GEVB ON Semiconductor, NCP1012GEVB Datasheet - Page 14

• Manufacturer Part Number: NCP1012GEVB
• Description: EVAL BOARD FOR NCP1012G
• Manufacturer: ON Semiconductor

Specifications of NCP1012GEVB

• Design Resources: NCP1012 Eval Brd BOM NCP1012GEVB Gerber Files NCP1012 Eval Brd Schematic
• Main Purpose: AC/DC, Primary Side
• Outputs And Type: 1, Isolated
• Voltage - Output: 12V
• Voltage - Input: 230VAC
• Regulator Topology: Flyback
• Frequency - Switching: 100kHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1012
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: NCP1012G
• Other names: NCP1012GEVBOS

Soft- -Start
activated during the power on sequence (PON). As soon as
V
increased from nearly zero up to the maximum internal
clamping level (e.g. 350 mA). This situation lasts 1.0 ms
and further to that time period, the peak current limit is
blocked to the maximum until the supply enters regulation.
The soft- -start is also activated during the over current burst
Non- -Latching Shutdown
temporarily and authorize its restart once the default has
disappeared. This option can easily be accomplished
through a single NPN bipolar transistor wired between FB
CC
The NCP101X features an internal 1.0 ms soft- -start
In some cases, it might be desirable to shut off the part
reaches VCC
Figure 23. A non- -latching shutdown where pulses are stopped as long as the NPN is biased.
Figure 22. Soft- -Start is activated during a startup sequence or an OCP condition.
ON/OFF
OFF
0 V (Fresh PON)
4.7 V (Overload)
V
Current
CC
, the peak current is gradually
Sense
or
http://onsemi.com
14
8.5 V
(OCP) sequence. Every restart attempt is followed by a
soft- -start activation. Generally speaking, the soft- -start will
be activated when V
power- -on sequence) or 4.7 V, the latch- -off voltage
occurring during OCP. Figure 22 portrays the soft- -start
behavior. The time scales are purposely shifted to offer a
better zoom portion.
1.0 ms
and ground. By pulling FB below the internal skip level
(Vskip), the output pulses are disabled. As soon as FB is
relaxed, the IC resumes its operation. Figure 23 depicts the
application example.
Max Ip
+
CV
cc
1
2
3
4
CC
ramps up either from zero (fresh
8
7
5
Drain