CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 29
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CDB44800
Manufacturer Part Number
CDB44800
Description
BOARD EVAL FOR CS44800 PWM CTRL
Manufacturer
Cirrus Logic Inc
Series
Popguard®r
Specifications of CDB44800
Amplifier Type
Class D
Output Type
8-Channel
Voltage - Supply
20 V ~ 50 V
Operating Temperature
-10°C ~ 70°C
Board Type
Fully Populated
Utilized Ic / Part
CS44800
Description/function
Audio DSPs
Operating Supply Voltage
5 V
Product
Audio Modules
For Use With/related Products
CS44800
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Max Output Power X Channels @ Load
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1532
CDB-44800
CDB-44800
DS632F1
DAI_SDINx
DAI_LRCK
DAI_SCLK
DAI_SDIN1
DAI_LRCK
DAI_SCLK
DAI_SDIN4
4.4.1.3
4.4.1.4
In the right-justified format, data is received most significant bit first and with the least significant bit pre-
sented on the last DAI_SCLK before the DAI_LRCK transition and is valid on the rising edge of
DAI_SCLK. For the right-justified format, the left channel data is presented when DAI_LRCK is high and
the right channel data is presented when DAI_LRCK is low. Either 16 bits per sample or 24 bits per sam-
ple are supported.
In One Line mode #1 format, data is received most significant bit first on the first DAI_SCLK after a
DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 128Fs
rate. DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sam-
pled as valid on the same clock edge as the most significant bit of the first data sample and must be held
high for 64 DAI_SCLK periods. Each time slot is 20 bits wide, with the valid data sample left-justified within
the time slot. Valid data lengths are 16, 18, or 20 bits. Valid samples rates for this mode are 32 kHz to
96 kHz.
MSB
MSB
PWMOUTA4
PWMOUTA1
20 clks
20 clks
Right-Justified Data Format
One Line Mode #1
Right-Justified Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample
16
24
LSB
LSB
15 14 13 12 11 10
MSB
Left Channel
PWMOUTA2
Figure 20. One Line Mode #1 Serial Audio Format
Left Channels
20 clks
Figure 19. Right-Justified Serial Audio Formats
64 clks
LSB
9
8
MSB
7
PWMOUTA3
6
20 clks
5
SCLK Rate(s)
32, 48, 64, 128, 256 Fs
48, 64, 128, 256 Fs
4
LSB
3
2
1
0
MSB
MSB
PWMOUTB1
PWMOUTB4
20 clks
20 clks
LSB
LSB
15 14 13 12 11 10
MSB
PWMOUTB2
Right Channels
20 clks
64 clks
Right Channel
LSB
9
MSB
PWMOUTB3
8
20 clks
7
6
5
LSB
4
3
CS44800
2
1
MSB
MSB
0
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