CDB44800 Cirrus Logic Inc, CDB44800 Datasheet - Page 24
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CDB44800
Manufacturer Part Number
CDB44800
Description
BOARD EVAL FOR CS44800 PWM CTRL
Manufacturer
Cirrus Logic Inc
Series
Popguard®r
Specifications of CDB44800
Amplifier Type
Class D
Output Type
8-Channel
Voltage - Supply
20 V ~ 50 V
Operating Temperature
-10°C ~ 70°C
Board Type
Fully Populated
Utilized Ic / Part
CS44800
Description/function
Audio DSPs
Operating Supply Voltage
5 V
Product
Audio Modules
For Use With/related Products
CS44800
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Max Output Power X Channels @ Load
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1532
CDB-44800
CDB-44800
24
Additional Features
4.3
DAI_MCLK
DAI_LRCK
DAI_SCLK
DAI_SDINx
SYS_CLK
XTO
XTI
•
•
•
•
•
•
•
•
•
Clock Generation
The sources for internal clock generation for the PWM processing are as follows:
•
•
Digital volume control with soft ramp.
Individual channel volume gain, attenuation and mute capability; +24 to -127 dB in 0.25 dB steps.
Master volume attenuation; +24 to -127 dB in 0.25 dB steps.
Peak Detect and Volume Limiter with programmable attack and release rates.
Signal-clipping interrupt indicator.
Contains a two-stage digital output filter for speaker impedance compensation.
Provides 7 programmable GPIO pins with interrupt generation for easily interfacing to a variety of com-
monly available power state parts. Interrupts can be masked.
Selectable over-sample rate for increased audio bandwidth.
Power supply clock output, PS_SYNC, with programmable divider
FsIn Domain:
FsOut Domain:
–
–
–
DAI_MCLK, minimum 128Fs
XTI/XTO (Fundamental or 3
Clock signal on XTI (VDX is used to set logic voltage level)
Digital Audio
Ratio Detect
Input Port
1, 1.5, 2,
3, 4, 6, 8
XTAL /
CLKIN
1,2,4,8
Emphasis
De-
Figure 13. CS44800 Data Flow Diagram (Single Channel Shown)
FsIn FsOut
128Fs
SRC
SRC_MCLK (128Fs)
Compensation
2-pole Load
Filter
2.25
Clock Control
Channel
Volume
rd
overtone crystal), or
1,1.5,
2,4
Volume
Master
(AM_FREQ_HOP)
Σ
AM Freq. Hop
PWM_MCLK
MOD_MCLK
Over Sample
(OSRATE)
mute
LIMITER
DETECT
PEAK
Over Sample
x2
(OSRATE)
Modulator
Multibit
Σ∆
PWM Engine
Feedback
PSR
Delay
Delay
CS44800
PWM_OUT+
PWM_OUT-
DS632F1