ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 9

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

7.2 Control Panel
Once the FPGA Firmware download is complete,
the development board Control Panel will
automatically be displayed (Figure 10).
The following section describes the function of
the pull-down selection tabs in the left-hand side
of the ADC08(D)XXXXDEV product Control
Panel.
dependent.
available features.
Ø Channel Selection
Ø Temp Sensor
Ø Hardware/Serial Control
o
o
o
o
o
o
o
I – Displays the data captured from the I-
channel only after acquiring samples.
Q- Displays the data captured from the
Q-channel only after acquiring samples.
I and Q – Displays the data captured
from I- and Q-channels in two windows
after acquiring samples.
I/Q Interleaved – Displays the data
captured from the I- and Q-channels
interleaved in a single window, after
acquiring samples.
mode is enabled.
This displays the die temperature of both
the FPGA and the ADC.
Hardware Pin Control – The ADC is
controlled by the logic states on the
dedicated control pins. The logic on
these pins is determined by the setting of
OUTV, OUTEDGE, DDR, DES and FSR,
as described below.
Serial Register Program – The ADC’s
registers are accessed through the
Extended Control Mode. In this mode,
the hardware pin control is disabled and
the programmable registers are available
for fine tuning.
Note that some functions are device
Figure 10. Control Panel window
Refer to the device datasheet for
Use when DES
Note:
available only when Hardware Pin Control is
selected.
Note:
available regardless of Hardware/Serial Control
setting.
Ø Out V
Ø OutEdge
Ø DDR
Ø DES
Ø FSR
Ø Standby
Ø PDQ
o
o
o
o
o
o
o
o
o
o
o
o
o
o
Low Amplitude – LVDS output voltage
amplitude is set to 510 mVpk-pk.
High Amplitude – LVDS output voltage
amplitude is set to 710 mVpk-pk.
Falling Edge – Data outputs are
changed on the falling edge of DCLK+
(SDR mode only).
Rising
changed on the rising edge of DCLK+
(SDR mode only).
Disable Dual Data Rate – DDR Mode is
disabled (data output follow OutEdge
Setting).
Enable Dual Data Rate – Data is
concurrent with rising and falling edge of
DCLK+. (This is the default mode for 1.5
GHz clock).
Disable Dual Edge Sample – DES
Mode is disabled, i.e. the I- and Q-
channels are independent.
Enable Dual Edge Sample – The I-
channel is sampled on the rising and
falling edge of the clock.
650mV Full Scale – Sets the full-scale
range to 650 mVpk-pk.
870mV Full Scale – Sets the full-scale
range to 870 mVpk-pk.
Disable Standby – Enable all on-board
power regulators.
Enable Standby – Board is put into
standby mode – All power is shutdown
except USB power.
Disable Q Shutdown – The ADC’s Q-
channel is powered up and active.
Enable Q Shutdown – The ADC’s Q-
channel is shutdown.
The Following Pull-down Tabs are
The Following Pull-down Tabs are
Edge
–
Data
outputs
are