ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 11

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

7.5 Capturing Waveforms
When the ADC has been properly configured, the
selected input(s) may be sampled by clicking the
Acquire pull-down menu and selecting Samples.
Alternately, press F1 then the Escape key. See
Figure 12 for a sample waveform.
8.1 Xilinx Virtex 4 FPGA
The ADC08(D)XXXXDEV development board
implements the Xilinx Virtex 4 XC4VLX15-
10SF363C FPGA for ADC control and data
capture. The FPGA firmware is loaded over the
USB port when the WaveVision software is
started.
supplemental documentation is available to users
upon request. Please contact your local National
Semiconductor
Representative.
8.2 LED functions
The function of the LEDs on the front panel of the
board (Figure 13) is as follows:
8.0 Appendix A - Hardware
Ø STB (STANDBY) - illuminates when the
Information
board is in standby mode.
Figure 12. Waveform capture example
The
Figure 13. LED front panel
Sales
FPGA
or
Verilog
Field
Applications
code
and
Ø TRG (TRIGGER EVENT) - illuminates
Ø OVR (ADC OVER-RANGE) - illuminates
Ø CLK (CLOCK INPUT) - flashes with 50%
Ø PWR (POWER) - illuminates when the
Ø UPL (UPLOAD) - illuminates when the
Ø SMP (SAMPLE) - illuminates when the
Ø IDL (IDLE) - illuminates when the system
when the Trigger Input makes low to high
transition.
when the I- or Q-channel exceeds the full-
scale range of the ADC.
duty cycle if the ADC is receiving a clock
input.
external 12V power supply is connected
and the system is not in Standby.
FPGA is uploading sample data to the PC.
FPGA is sampling data and storing to the
FIFO buffers.
is IDLE.
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