ADC08500DEV/NOPB National Semiconductor, ADC08500DEV/NOPB Datasheet - Page 12

• Manufacturer Part Number: ADC08500DEV/NOPB
• Description: BOARD DEV FOR ADC08D500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08500DEV/NOPB

• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 800mW @ 500MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADC08500DEV

8.3 Expansion Header
A 72-pin Future Bus Expansion Header (Table 3)
is provided on the rear panel to allow easy
connection to a third-party microprocessor board
to allow for the reading and analysis of the data
captured by the FPGA.
The Data busses on this header may be
configured as follows:
PIN
P1_A1
P1_A2
P1_A3
P1_A4
P1_A5
P1_A6
P2_A1
P2_A2
P2_A3
P2_A4
P2_A5
P2_A6
P3_A1
P3_A2
P3_A3
P3_A4
P3_A5
P3_A6
P1_C1
P1_C2
P1_C3
P1_C4
P1_C5
P1_C6
P2_C1
P2_C2
P2_C3
P2_C4
P2_C5
P2_C6
P3_C1
P3_C2
P3_C3
P3_C4
P3_C5
P3_C6
DESCRIPTION
I2C – SDA
I2C – SCL
SSP – SERIAL DATA
SSP – SERIAL CLOCK
FPGA RESET
READ FIFO
WRITE FIFO
FIFO FULL
FIFO EMPTY
ADC DCLK RESET
FPGA CONF DONE
FPGA JTAG – TMS
FPGA JTAG – TCK
FPGA JTAG – TDI
FPGA JTAG – TDO
Not SHUTDOWN
3.3V SUPPLY
12V SUPPLY
DATA BUS A P0 (LVDS or CMOS)
DATA BUS A P1 (LVDS or CMOS)
DATA BUS A P2 (LVDS or CMOS)
DATA BUS A P3 (LVDS or CMOS)
DATA BUS A P4 (LVDS or CMOS)
DATA BUS A P5 (LVDS or CMOS)
DATA BUS A P6 (LVDS or CMOS)
DATA BUS A P7 (LVDS or CMOS)
INPUT STROBE P
DATA BUS B P0 (LVDS or CMOS)
DATA BUS B P1 (LVDS or CMOS)
DATA BUS B P2 (LVDS or CMOS)
DATA BUS B P3 (LVDS or CMOS)
DATA BUS B P4 (LVDS or CMOS)
DATA BUS B P5 (LVDS or CMOS)
DATA BUS B P6 (LVDS or CMOS)
DATA BUS B P7 (LVDS or CMOS)
OUTPUT STROBE P
Table 3. Future bus expansion header pins
PIN
P1_B1
P1_B2
P1_B3
P1_B4
P1_B5
P1_B6
P2_B1
P2_B2
P2_B3
P2_B4
P2_B5
P2_B6
P3_B1
P3_B2
P3_B3
P3_B4
P3_B5
P3_B6
P1_D1
P1_D2
P1_D3
P1_D4
P1_D5
P1_D6
P2_D1
P2_D2
P2_D3
P2_D4
P2_D5
P2_D6
P3_D1
P3_D2
P3_D3
P3_D4
P3_D5
P3_D6
All control signals on pins A1 to A15 will be at
LVCMOS 3.3V levels.
DESCRIPTION
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
DATA BUS A N0 (LVDS or CMOS)
DATA BUS A N1 (LVDS or CMOS)
DATA BUS A N2 (LVDS or CMOS)
DATA BUS A N3 (LVDS or CMOS)
DATA BUS A N4 (LVDS or CMOS)
DATA BUS A N5 (LVDS or CMOS)
DATA BUS A N6 (LVDS or CMOS)
DATA BUS A N7 (LVDS or CMOS)
INPUT STROBE N
DATA BUS B N0 (LVDS or CMOS)
DATA BUS B N1 (LVDS or CMOS)
DATA BUS B N2 (LVDS or CMOS)
DATA BUS B N3 (LVDS or CMOS)
DATA BUS B N4 (LVDS or CMOS)
DATA BUS B N5 (LVDS or CMOS)
DATA BUS B N6 (LVDS or CMOS)
DATA BUS B N7 (LVDS or CMOS)
OUTPUT STROBE N
Ø Two 8-bit busses with LVDS differential
Ø Four 8-bit busses with LVCMOS (3.3V
signaling, plus two LVDS strobes.
I/O) signaling plus four CMOS strobes.
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