ADC08500DEV/NOPB National Semiconductor, ADC08500DEV/NOPB Datasheet - Page 10

• Manufacturer Part Number: ADC08500DEV/NOPB
• Description: BOARD DEV FOR ADC08D500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08500DEV/NOPB

• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 800mW @ 500MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08500
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: ADC08500DEV

7.3 Serial Control Mode
When the Hardware/Serial Control tab is selected
as Serial Register Program, the control panel
display will enable the other bits (Figure 11).
In this mode, the register settings may be
changed simply by clicking on the bits. Doing so
will toggle each bit value. Any linear values such
as Full Scale Range or Offset will automatically
be updated.
Ø DC_Coup
Ø Ext_Clock
Ø Reset FPGA
Ø Calibrate ADC
o
o
o
o
o
o
o
o
Figure 11. Serial Register Program window
Disable Shutdown – The ADC is
powered up and active.
Enable Shutdown – The ADC is put into
low power mode. Register Settings are
retained.
AC Coupling – The I-channel is AC-
coupled to the ADC’s input.
DC Coupling – The I-channel is DC-
coupled to the ADC’s input (not available
in AC only mode.)
Internal Clock – The ADC is clocked
using the on-board clock.
External Clock – The ADC is clocked
from an external clock source which is
connected to the “CLOCK” input.
This button resets the FPGA, and also
returns all the pull-down tabs to their
default values.
This button issues an on-command
calibration to the ADC by toggling the
ADC’s calibrate pin.
The Reset Registers button at the bottom of the
Control Panel will reset and write all the values to
the power-on default settings.
Note: Please refer to the ADC08(D)XXXX
datasheet for a full description of the ADC’s
internal registers.
7.4 Manually downloading the FPGA
Although the WaveVision software is designed to
automatically recognize the development board
and download the appropriate FPGA code into it,
it is possible for the user to download a different
FPGA code (the .bit file) into the board. To
download another FPGA code into the board,
follow the subsequent instructions:
Please note that the development board's
operation is only assured for the FPGA code
provided by National. Though the board makes it
possible for the user to develop and test his own
FPGA code, such operation is not supported by
National.
1. Place the desired .bit file (Xilinx object
2. Start WaveVision with the board connected
3. The default FPGA will load automatically –
4. From the main WaveVision panel, under
5. Click the Xilinx Image Settings button
6. Deselect the Select Images automatically
7. Then click the Browse button and select
8. Click the Accept button. The Select Xilinx
9. Load the FPGA image by clicking on the
10. FPGA bit file download may be confirmed
code that is known to operate correctly for
the development board you are using) in a
known directory of your choice on the C:
drive.
via the USB.
this will be overwritten.
the Settings drop down menu, select
Capture Settings. This will bring up
another panel called System Settings.
within the System Settings panel. This will
bring up another panel labeled Select
Xilinx Firmware.
button.
the location of the bit file.
Firmware panel will disappear.
Reset (or Test in some versions) button. It
may be found in the Communication sub-
panel of the System Settings panel.
by observing the progress bar pop-up. If
the progress bar goes half-way and
suddenly terminates, the FPGA has not
loaded. The second half should progress at
a similar rate.
firmware