CDB53L21 Cirrus Logic Inc, CDB53L21 Datasheet - Page 25

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CDB53L21

Manufacturer Part Number
CDB53L21
Description
BOARD EVAL FOR CS53L21 ADC
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB53L21

Number Of Adc's
2
Number Of Bits
24
Sampling Rate (per Second)
96k
Data Interface
Serial
Inputs Per Adc
3 Single Ended
Input Range
±2.5 V
Power (typ) @ Conditions
22.45mW @ 48kSPS, 2.5 V
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Utilized Ic / Part
CS53L21
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1550
DS700PP1
4.3.5
4.3.6
Analog Input Multiplexer
A stereo 4-to-1 analog input multiplexer selects between a line-level input source, or a mic-level input
source, depending on the PDN_PGAx and AINx_MUX[1:0] bit settings. Signals may be routed to or by-
passed around the PGA. To conserve power, the PGA’s may be powered down allowing the user to select
from multiple line-level sources and route the stereo signal directly to the ADC. When using the MIC pre-
amp, however, the PGA must be powered up.
Analog input channel B may also be used as an output for the MIC bias voltage. The MICBIAS_SEL bit
routes the bias voltage to either of two pins. The multiplexer must then select from the remainder of the
two input channels.
The ADC, PGA and MIC pre-amplifier each has an associated input resistance. When selecting between
these paths, the input resistance to the A/D will change accordingly. Refer to the input resistance charac-
teristics in the
MIC & PGA Gain
The MIC-level input passes through a +16 dB or +32 dB analog gain stage prior to the input multiplexer,
allowing it to be used for microphone level signals without the need for any external gain. The PGA must
be powered up when using the MIC pre-amp.
The PGA stage provides an additional +12 dB to -3 dB of analog gain in 0.5 dB steps.
Software
Controls:
Software
Controls:
Characteristic and Specification Tables
“Power Control 1 (Address 02h)” on page
Input Select, Invert & Mute (Address 07h)” on page
“Power Control 1 (Address 02h)” on page
page
page
47,
49,
“ALCX & PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)” on
“MIC Control (Address 05h)” on page
40,
40,
for the input resistance of each path.
“ADCx Input Select, Invert & Mute (Address 07h)” on
“MIC Control (Address 05h)” on page 44 “ADCx
44.
47.
CS53L21
25

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