CDB5532U Cirrus Logic Inc, CDB5532U Datasheet - Page 38

• Manufacturer Part Number: CDB5532U
• Description: BOARD EVAL FOR CS5532U ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5532U

• Number Of Adc's: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 35mW @ 3.84kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5532
• Description/function: Audio DSPs
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: C8051F320
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1159

2.9. Digital Filter
The CS5532/34 have linear phase digital filters
which are programmed to achieve a range of output
word rates (OWRs) as stated in the Channel-Setup
Register Descriptions section. The ADCs use a
Sinc
and 3840 Sps (MCLK = 4.9152 MHz). Other out-
put word rates are achieved by using the Sinc
followed by a Sinc
decimation rate. Figure 16 shows the magnitude re-
sponse of the 60 Sps filter, while Figures 17 and 18
show the magnitude and phase response of the filter
at 120 Sps. The Sinc
rates except for the 3200 Sps and 3840 Sps
38
Figure 16. Digital Filter Response (WR = 60 Sps)
Figure 18. 120 Sps Filter Phase Plot to 120 Hz
5
-120
digital filter to output word rates at 3200 Sps
-40
-80
-180
0
180
-90
90
0
0
0
60
30
3
3
( )
Frequency (Hz)
Frequency (Hz)
filter with a programmable
is active for all output word
120
Sin x
x
60
180
3
240
90
300
5
120
filter
(MCLK = 4.9152 MHz) rate. The Z-transforms of
the two filters are shown in Figure 19. For the Sinc
filter, “D” is the programmable decimation ratio,
which is equal to 3840/OWR when FRS = 0 and
3200/OWR when FRS = 1.
The converter’s digital filters scale with MCLK.
For example, with an output word rate of 120 Sps,
the filter’s corner frequency is at 31 Hz. If MCLK
is increased to 5.0 MHz, the OWR increases by
1.0175% and the filter’s corner frequency moves to
31.54 Hz. Note that the converter is not specified to
run at MCLK clock frequencies greater than
5 MHz.
Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz
Note:
Sinc
Sinc
Figure 19. Z-Transforms of Digital Filters
5
3
=
=
-120
-40
-80
(
------------------------- -
(
(
------------------------ -
(
0
1 z
1 z
1 z
1 z
See the text regarding the Sinc
decimation ratio “D”.
–
–
–
–
0
–
–
–
1 –
Frequency
80
16
D
)
)
10
12
14
16
19
32
)
)
2
4
6
8
3
3
Flatness
5
5
×
(
------------------------- -
(
1 z
-0.01
-0.05
-0.11
-0.19
-0.30
-0.43
-0.59
-0.77
-1.09
-3.13
1 z
dB
–
–
Frequency (Hz)
40
–
4 –
16
)
)
3
3
×
CS5532/34-BS
(
-----------------------
(
1 z
1 z
–
–
80
4 –
2 –
)
)
2
2
×
(
-----------------------
(
3
1 z
1 z
filter’s
–
–
DS755F3
2 –
1 –
120
)
)
3
3
3