EVAL-AD7664CBZ Analog Devices Inc, EVAL-AD7664CBZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD7664CBZ
• Description: BOARD EVALUATION FOR AD7664
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7664CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 570k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 115mW @ 500kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7664
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7664
Pin No.
16
17
18
19
20
21
22
23
24
25–28
29
30
31
32
33
34
D7
or RDC/SDIN
OGND
OVDD
DVDD
DGND
D8
or SDOUT
D9
or SCLK
D10
or SYNC
D11
or RDERROR
D[12:15]
BUSY
DGND
RD
CS
RESET
PD
Mnemonic
Type
DI/O
P
P
P
P
DO
DI/O
DO
DO
DO
DO
P
DI
DI
DI
DI
Description
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
Digital Power. Nominally at 5 V.
Digital Power Ground.
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard-
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external
data input or a Read Mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is
HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the
data can be output on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground.
interface (5 V or 3 V).
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7664
provides the conversion result, MSB first, from its internal shift register. The DATA format
is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is
valid on both edges of SCLK.
In Serial Mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the
next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next
rising edge.
When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data
Output Bus.
When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output
frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When
a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains
HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC
is HIGH, SYNC is driven LOW and remains LOW while the SDOUT output is valid.
When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is
used as an incomplete read error flag. In Slave Mode, when a data read is started and not
complete when the following conversion is complete, the current data is lost and RDERROR
is pulsed HIGH.
less of the state of SER/PAR.
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data-ready clock signal.
Must Be Tied to Digital Ground.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. CS is also used to gate the external clock.
Reset Input. When set to a logic HIGH, reset the AD7664. Current conversion if any is aborted.
If not used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited after the current one is completed.
–6–
REV. E