EVAL-AD7664CBZ Analog Devices Inc, EVAL-AD7664CBZ Datasheet - Page 16

• Manufacturer Part Number: EVAL-AD7664CBZ
• Description: BOARD EVALUATION FOR AD7664
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7664CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 570k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 115mW @ 500kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7664
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7664
DATABUS
CNVST,
Figure 15. Slave Parallel Data Timing for Reading
(Read during Convert)
CS = 0
BUSY
RD
SDOUT
CS, RD
CNVST
CNVST
SDOUT
CS, RD
BUSY
SYNC
SCLK
BUSY
SYNC
SCLK
Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
t
12
t
3
t
CONVERSION
16
PREVIOUS
t
1
Figure 16. Master Serial Data Timing for Reading (Read after Convert)
t
t
3
13
t
t
t
14
15
16
t
t
t
14
15
29
t
17
X
t
t
18
22
t
4
EXT/INT = 0
t
EXT/INT = 0
1
t
D15
3
X
t
t
1
20
22
t
19
t
21
t
20
D14
t
D15
2
23
1
t
19
t
18
RDC/SDIN = 0
RDC/SDIN = 1
D14
t
2
t
21
3
23
–16–
t
28
SERIAL INTERFACE
The AD7664 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7664 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7664 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. The AD7664
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted, if desired. Depending on RDC/SDIN input,
the data can be read after each conversion or during the fol-
lowing conversion. Figures 16 and 17 show the detailed timing
diagrams of these two modes.
3
INVSCLK = INVSYNC = 0
14
D2
INVSCLK = INVSYNC = 0
14
D2
15
D1
15
D1
16
t
24
16
t
30
D0
t
D0
24
t
t
t
t
t
t
26
25
27
25
26
27
REV. E