KDC5512H-Q48EVAL Intersil, KDC5512H-Q48EVAL Datasheet - Page 3

• Manufacturer Part Number: KDC5512H-Q48EVAL
• Description: DAUGHTER CARD FOR KAD5512
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KDC5512H-Q48EVAL

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 250M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 1.47 Vpp
• Power (typ) @ Conditions: 429mW @ 250MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: KAD5512HP-25, KMB001 Motherboard
• For Use With: KMB001LEVAL - MOTHERBOARD FOR LVDS ADC CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table of Contents
Absolute Maximum Ratings ......................................... 4
Thermal Information...................................................... 4
Operating Conditions.................................................... 4
Electrical Specifications ............................................... 4
Digital Specifications .................................................... 6
Timing Diagrams ........................................................... 7
Switching Specifications .............................................. 8
Pinout/Package Information......................................... 9
Typical Performance Curves ........................................ 14
Theory of Operation ...................................................... 17
Pin Descriptions - 72QFN........................................... 9
Pinout ......................................................................... 11
Pin Descriptions - 48QFN........................................... 12
Pinout ......................................................................... 13
Functional Description ................................................ 17
Power-On Calibration ................................................. 17
User-Initiated Reset.................................................... 18
Analog Input ............................................................... 18
Clock Input ................................................................. 19
Jitter............................................................................ 20
Voltage Reference...................................................... 20
Digital Outputs ............................................................ 20
Over-Range Indicator ................................................. 20
Power Dissipation....................................................... 20
Nap/Sleep................................................................... 21
Data Format ............................................................... 21
3
KAD5512HP
Serial Peripheral Interface ........................................... 22
Equivalent Circuits ....................................................... 29
72 Pin/48 Pin Package Options ................................... 30
ADC Evaluation Platform ............................................. 31
Layout Considerations................................................. 31
Definitions ..................................................................... 31
Revision History ........................................................... 32
Package Outline Drawings........................................... 33
SPI Physical Interface................................................ 23
SPI Configuration....................................................... 24
Device Information ..................................................... 24
Indexed Device Configuration/Control ....................... 24
Global Device Configuration/Control.......................... 25
Device Test ................................................................ 27
SPI Memory Map ....................................................... 28
Split Ground and Power Planes................................. 31
Clock Input Considerations ........................................ 31
Exposed Paddle......................................................... 31
Bypass and Filtering .................................................. 31
LVDS Outputs ............................................................ 31
LVCMOS Outputs ...................................................... 31
Unused Inputs............................................................ 31
L48.7x7E.................................................................... . 33
L72.10x10D................................................................ . 34
October 1, 2009
FN6808.3