DS26524DK Maxim Integrated Products, DS26524DK Datasheet - Page 231

• Manufacturer Part Number: DS26524DK
• Description: KIT DESIGN FOR DS26524
• Manufacturer: Maxim Integrated Products

Specifications of DS26524DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: DS26524
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts.
Bit 6: BERT Bit-Error-Detected Event (BBED). A latched bit that is set when a bit error is detected. The receive
BERT must be in synchronization for it to detect bit errors.
Bit 5: BERT Bit Counter Overflow Event (BBCO). A latched bit that is set when the 32-bit BERT bit counter
(BBC) overflows.
Bit 4: BERT Error Counter Overflow Event (BECO). A latched bit that is set when the 24-bit BERT error counter
(BEC) overflows.
Bit 3: BERT Receive All-Ones Condition (BRA1). A latched bit that is set when 32 consecutive ones are
received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). A latched bit that is set when 32 consecutive zeros are
received.
Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS). A latched bit that is set whenever the
receive BERT begins searching for a pattern.
Bit 0: BERT in Synchronization Condition (BSYNC). Will be set when the incoming pattern matches for 32
consecutive bit positions.
—
7
0
BLSR
BERT Latched Status Register
110Eh + (10h x n): where n = 0 to 3, for Ports 1 to 4
BBED
6
0
BBCO
5
0
231 of 273
BECO
0
4
BRA1
3
0
BRA0
2
0
BRLOS
1
0
BSYNC
0
0