DS26524DK Maxim Integrated Products, DS26524DK Datasheet - Page 221
DS26524DK
Manufacturer Part Number
DS26524DK
Description
KIT DESIGN FOR DS26524
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26524G.pdf
(273 pages)
Specifications of DS26524DK
Main Purpose
Telecom, Framer and Line Interface Units (LIUs)
Utilized Ic / Part
DS26524
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts.
Bit 7: Jitter Attenuator Limit Trip Clear (JALTC). This latched bit is set when a jitter attenuator limit trip condition
was detected and then removed.
Bit 6: Open-Circuit Clear (OCC). This latched bit is set when an open-circuit condition was detected at TTIP and
TRING and then removed.
Bit 5: Short-Circuit Clear (SCC). This latched bit is set when a short-circuit condition was detected at TTIP and
TRING and then removed.
Bit 4: Loss of Signal Clear (LOSC). This latched bit is set when a loss-of-signal condition was detected at RTIP
and RRING and then removed.
Bit 3: Jitter Attenuator Limit Trip Set (JALTS). This latched bit is set when the jitter attenuator limit trip condition
is detected.
Bit 2: Open-Circuit Detect (OCD). This latched bit is set when an open-circuit condition is detected at TTIP and
TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).
Bit 1: Short-Circuit Detect (SCD). This latched bit is set when a short-circuit condition is detected at TTIP and
TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).
Bit 0: Loss of Signal Detect (LOSD). This latched bit is set when an LOS condition is detected at RTIP and
RRING.
JALTC
7
0
LLSR
LIU Latched Status Register
1005h + (20h x n): where n = 0 to 3, for Ports 1 to 4
OCC
6
0
SCC
5
0
221 of 273
LOSC
0
4
JALTS
3
0
OCD
2
0
SCD
1
0
LOSD
0
0
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