DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 5
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DS26528DK
Manufacturer Part Number
DS26528DK
Description
KIT DESIGN FOR DS26528
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26528G.pdf
(276 pages)
Specifications of DS26528DK
Main Purpose
Telecom, Framer and Line Interface Units (LIUs)
Utilized Ic / Part
G575DS26528
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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DS26528 Octal T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 6-1. Block Diagram ......................................................................................................................................... 17
Figure 6-2. Detailed Block Diagram........................................................................................................................... 18
Figure 8-1. Backplane Clock Generation................................................................................................................... 28
Figure 8-2. Device Interrupt Information Flow Diagram............................................................................................. 31
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz ...................................................................................... 36
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz ...................................................................................... 37
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz .................................................................................... 38
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode................................................................................................... 42
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode ....................................................................... 43
Figure 8-8. CRC-4 Recalculate Method .................................................................................................................... 64
Figure 8-9. Receive HDLC Example.......................................................................................................................... 70
Figure 8-10. HDLC Message Transmit Example....................................................................................................... 72
Figure 8-11. Basic Balanced Network Connections .................................................................................................. 74
Figure 8-12. T1/J1 Transmit Pulse Templates .......................................................................................................... 78
Figure 8-13. E1 Transmit Pulse Templates ............................................................................................................... 79
Figure 8-14. Typical Monitor Application ................................................................................................................... 81
Figure 8-15. Jitter Attenuation ................................................................................................................................... 83
Figure 8-16. Analog Loopback................................................................................................................................... 84
Figure 8-17. Local Loopback ..................................................................................................................................... 84
Figure 8-18. Remote Loopback ................................................................................................................................. 85
Figure 8-19. Dual Loopback ...................................................................................................................................... 85
Figure 9-1. Register Memory Map for the DS26528.................................................................................................. 89
Figure 10-1. T1 Receive-Side D4 Timing ................................................................................................................ 235
Figure 10-2. T1 Receive-Side ESF Timing.............................................................................................................. 235
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................... 236
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled).............................................. 236
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled).............................................. 237
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode.................................................................. 238
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode .............................................................. 239
Figure 10-8. T1 Transmit-Side D4 Timing ............................................................................................................... 240
Figure 10-9. T1 Transmit-Side ESF Timing............................................................................................................. 240
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................ 241
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 241
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 242
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode............................................................... 243
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode.................................................................... 244
Figure 10-15. E1 Receive-Side Timing.................................................................................................................... 245
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 245
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 246
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 246
Figure 10-19. E1 Transmit-Side Timing................................................................................................................... 247
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 247
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 248
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 248
Figure 10-23. E1 G.802 Timing ............................................................................................................................... 249
Figure 12-1. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 253
Figure 12-2. Intel Bus Write Timing (BTS = 0)......................................................................................................... 253
Figure 12-3. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 254
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