DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 178
DS26528DK
Manufacturer Part Number
DS26528DK
Description
KIT DESIGN FOR DS26528
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26528G.pdf
(276 pages)
Specifications of DS26528DK
Main Purpose
Telecom, Framer and Line Interface Units (LIUs)
Utilized Ic / Part
G575DS26528
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are real time.
Bits 6 to 4: Receive Packet Status (PS[2:0]). These are real-time bits indicating the status as of the last read of
the receive FIFO.
Bit 1: Receive FIFO Above High Watermark Condition (RHWM). Set when the receive 64-byte FIFO fills beyond
the high watermark as defined by the Receive HDLC FIFO Control register (RHFC). This is a real-time bit.
Bit 0: Receive FIFO Not Empty Condition (RNE). Set when the receive 64-byte FIFO has at least one byte
available for a read. This is a real-time bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Message Status (MS).
Bits 6 to 0: Receive FIFO Packet Bytes Available Count (RPBA[6:0]). RPBA0 is the LSB.
PS2
0
0
0
0
1
0 = Bytes indicated by RPBA[6:0] are the end of a message. Host must check the HDLC status register for
details.
1 = Bytes indicated by RPBA[6:0] are the beginning or continuation of a message. The host does not need
to check the HDLC status. The MS bit returns to a value of 1 when the Rx HDLC FIFO is empty.
PS1
0
0
1
1
0
MS
—
7
0
7
0
PS0
0
1
0
1
0
In Progress: End of message has not yet been reached.
Packet OK: Packet ended with correct CRC codeword.
CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword.
Abort: Packet ended because an abort signal was detected (7 or more ones in a row).
Overrun: HDLC controller terminated reception of packet because receive FIFO is full.
RRTS5
Receive Real-Time Status Register 5 (HDLC)
0B4h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RHPBA
Receive HDLC Packet Bytes Available Register
0B5h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RPBA6
PS2
6
0
6
0
RPBA5
PS1
5
0
5
0
RPBA4
178 of 276
PS0
4
0
4
0
PACKET STATUS
RPBA3
—
3
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
RPBA2
—
2
0
2
0
RPBA1
RHWM
1
0
1
0
RPBA0
RNE
0
0
0
0
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