DS3112DK Maxim Integrated Products, DS3112DK Datasheet - Page 10

• Manufacturer Part Number: DS3112DK
• Description: KIT DEMO FOR DS3112
• Manufacturer: Maxim Integrated Products

Specifications of DS3112DK

• Main Purpose: Interface, Crosspoint Switch/Multiplexer
• Utilized Ic / Part: DS3112
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.2.6 BERT
1.2.7 Diagnostics
1.2.8 Control Port
1.2.9 Packaging and Power
Can generate and detect the pseudorandom patterns of 2
repetitive patterns from 1 to 32 bits in length
BERT is a global chip resource that can be used either in the T3/E3 data path or in any one of the T1
or E1 data paths
Large error counter (24 bits) allows testing to proceed for long periods without Host intervention
Errors can be inserted into the generated BERT patterns for diagnostic purposes
T3/E3 and T1/E1 diagnostic loopbacks (transmit to receive)
T3/E3 and T1/E1 line loopbacks (receive to transmit)
T3/E3 payload loopback
T3/E3 errors counters for: BiPolar Violations (BPV), Code Violations (CV), Loss Of Frame (LOF),
framing bit errors (F, M or FAS), EXcessive Zeros (EXZ), T3 Parity bits, T3 C-Bit Parity, and Far
End Block Errors (FEBE)
Error counters can be either updated automatically on one second boundaries as timed by the DS3112
or via software control or via an external hardware pulse
Can insert the following T3/E3 errors: BiPolar Violations (BPV), EXcessive Zeros (EXZ), T3 Parity
bits, T3 C-Bit Parity, framing bit errors (F, M, or FAS)
Inserted errors can be either controlled via software or via an external hardware pulse
Generates T2/E2 Loss Of Frame (LOF)
Nonmultiplexed or multiplexed 16-bit control port (with an optional 8-bit mode)
Intel and Motorola Bus compatible
3.3V low-power CMOS with 5V tolerant inputs and outputs
256-pin plastic BGA package (27mm x 27mm)
IEEE 1149.1 JTAG test port
10 of 133
7
- 1, 2
11
- 1, 2
15
- 1 and QRSS as well as
DS3112