DS2148DK Maxim Integrated Products, DS2148DK Datasheet - Page 31

• Manufacturer Part Number: DS2148DK
• Description: KIT DESIGN LIU DS2148 3/5V T1/E1
• Manufacturer: Maxim Integrated Products

Specifications of DS2148DK

• Main Purpose: Telecom, Line Interface Units (LIUs)
• Utilized Ic / Part: DS2148
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.1 Device Power-Up and Reset
The DS2148 will reset itself upon power-up, setting all writeable registers to 00h and clearing the status
and information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After
the power supplies have settled following power-up, initialize all control registers to the desired settings,
then toggle the LIRST bit (CCR3.2). The DS2148 can be reset at anytime to the default settings by
bringing HRST (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
Table 4-2. Receive Sensitivity Settings
(CCR4.4)
(MSB)
SYMBOL
L2
EGL
JABDS
0
1
1
0
EGL
DJA
TPD
JAS
L2
L1
L0
L1
(CCR1.7)
0 (E1)
0 (E1)
1 (T1)
1 (T1)
ETS
POSITION
CCR4.7
CCR4.6
CCR4.5
CCR4.4
CCR4.3
CCR4.2
CCR4.1
CCR4.0
L0
-12dB (short haul)
-43dB (long haul)
-30dB (limited long haul)
-36dB (long haul)
RECEIVE SENSITIVITY
DESCRIPTION
Line Build-Out Select Bit 2. Sets the transmitter build out
(Table 7-1
Line Build-Out Select Bit 1. Sets the transmitter build out
(Table 7-1
Line Build-Out Select Bit 0. Sets the transmitter build out
(Table 7-1
Receive Equalizer Gain Limit. This bit controls the sensitivity
of the receive equalizer
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the TTIP and
TRING pins
EGL
31 of 73
for E1 and
for E1 and
for E1 and
JAS
Table 7-2
Table 7-2
Table 7-2
(Table
JABDS
4-2).
for T1)
for T1)
for T1)
DJA
(LSB)
TPD