DS2148DK Maxim Integrated Products, DS2148DK Datasheet - Page 16

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DS2148DK

Manufacturer Part Number
DS2148DK
Description
KIT DESIGN LIU DS2148 3/5V T1/E1
Manufacturer
Maxim Integrated Products
Datasheets

Specifications of DS2148DK

Main Purpose
Telecom, Line Interface Units (LIUs)
Utilized Ic / Part
DS2148
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
TTIP/TRING
NAME
TNEG
TCLK
TPOS
TEST
VSM
SDO
V
SDI
V
DD
SS
34/37
21/36
22/35
PIN
43
26
42
41
20
6
7
I/O
O
O
I
I
I
I
I
-
I
-
Serial Data Input. Sampled on rising edge (ICES = 0) or the falling edge
(ICES = 1) of SCLK.
Serial Data Output. Valid on the falling edge (OCES = 0) or the rising
edge (OCES = 1) of SCLK.
Transmit Clock. A 2.048 MHz or 1.544 MHz primary clock. Used to
clock data through the transmit side formatter. Can be sourced internally
by MCLK or RCLK. See Common Control Register 1 and
Tri-State Control. Set high to tri-state all outputs and I/O pins (including
the parallel control port). Set low for normal operation. Useful in board
level testing.
Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or
the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto
the line.
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the
rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the
line.
Transmit Tip and Ring . Analog line driver outputs. These pins connect
via a step-up transformer to the line. See Section
5.0V ±5% Positive Supply
Voltage Supply Mode. Should be tied high for 5V operation.
Signal Ground
16 of 73
FUNCTION
5
for details.
Figure
1-3.

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