SI5364-EVB Silicon Laboratories Inc, SI5364-EVB Datasheet - Page 9

• Manufacturer Part Number: SI5364-EVB
• Description: BOARD EVALUATION FOR SI5364
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5364-EVB

• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: SI5364
• Processor To Be Evaluated: SI5364
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1146

Table 4. AC Characteristics (PLL Performance Characteristics)
(V
Table 3. AC Characteristics (Continued)
(V
Wander/Jitter at 800 Hz Bandwidth
(BWSEL[1:0] = 10)
Jitter Tolerance (See Figure 8)
CLKOUT RMS Jitter Generation
FEC[1:0] = 00 (1/1 Scaling)
Notes:
Parameter
SYNCIN Pulse Width
FSYNC Frequency
FSYNC Pulse Width
SYNCIN to FSYNC
Phase Skew Between Outputs
RSTN/CAL Pulse Width
INCDELAY, DECDELAY Pulse
Width
INCDELAY, DECDELAY Setup Time
INCDELAY, DECDELAY Hold Time
Transitionless Period Required on
CLKIN for Detecting an LOS Condi-
tion
Recovery Time for Clearing an LOS
or FOS Condition
VALTIME = 0
VALTIME = 1
*Note: The Si5364 provides a 1, 8, or 32x clock frequency multiplication function with an option for additional frequency
DD33
DD33
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
= 3.3 V ± 5%, TA = –20 to 85 °C)
= 3.3 V ±5%, T
of nanoseconds per millisecond. The equivalent ps/ μ s unit is used here since the maximum phase transient magnitude
for the Si5364 (t
scaling by a factor of 255/238 or 238/255 for FEC rate compatibility.
Parameter
A
PT_MTIE
= –20 to 85 °C)
) never reaches one nanosecond.
t
t
FSYNC_PW
SYNCIN_DL
Symbol
t
t
f
t
SYNCIN
INCDEC
t
t
FSYNC
SETUP
t
HOLD
RSTN
t
t
skew
LOS
VAL
Y
J
Symbol
J
GEN(RMS)
TOL(PP)
applied until the applica-
Measured from when a
valid reference clock is
Rev. 2.5
ble LOS or FOS flag
Test Condition
Figure 3
Figure 3
Figure 3
Figure 3
Figure 5
Figure 5
Figure 5
Figure 4
clears
12 kHz to 20 MHz
50 kHz to 80 MHz
Test Condition
f = 800 Hz
f = 80 Hz
f = 8 Hz
f
O_622
0.09
12.0
Min
24/
20
38
20
—
—
—
1
1
1
16
1000
Min
f
100
2430
10
O_19
—
—
Typ
/f
—
45
—
—
—
—
—
—
—
—
O_19
/
0.87
0.26
Typ
—
—
—
f
Si5364
O_622
Max
0.22
14.1
400
32/
52
—
—
—
—
—
—
—
Max Unit
0.35
1.2
—
—
—
Unit
kHz
ns
ns
ps
ns
μ s
μ s
μ s
s
s
s
ns
ns
ns
ps
ps
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