SI5364-EVB Silicon Laboratories Inc, SI5364-EVB Datasheet - Page 33

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SI5364-EVB

Manufacturer Part Number
SI5364-EVB
Description
BOARD EVALUATION FOR SI5364
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI5364-EVB

Main Purpose
Timing, Clock Generator
Utilized Ic / Part
SI5364
Processor To Be Evaluated
SI5364
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1146
Si5364
Table 10. Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
C5
FXDDELAY
I*
LVTTL
Fixed Delay Control.
Active high input that fixes the clock input to clock
output phase relationship to a constant value. When
this pin is high and the device is operating in manual
select mode (AUTOSEL = 0), hitless recovery from
digital hold is disabled, and the input to output phase
relationship will remain fixed as long as the
MANCNTRL[1:0] pins remain unchanged.
This feature is useful in applications that utilize a
single clock source and require a known input-to-
output phase relationship. The FXDDELAY input is
ignored when AUTOSEL is high.
*Note: The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
Rev. 2.5
33

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