SI3056PPT2-EVB Silicon Laboratories Inc, SI3056PPT2-EVB Datasheet
SI3056PPT2-EVB
Specifications of SI3056PPT2-EVB
Related parts for SI3056PPT2-EVB
SI3056PPT2-EVB Summary of contents
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Description The Si30xxPPT-EVB provides the telecommunications system engineer an easy way to evaluate the functionality of Silicon Laboratories’ Si30xx ...
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Si30xxPPT-EVB Functional Description The Si30xxPPT-EVB provides the telecommunications system engineer an easy way to evaluate the Si30xx solution. Silicon Labs’ DAAs are integrated direct access arrangements that provide a digital, low-cost, solid-state interface to worldwide telephone lines. Through the patented ...
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Configuring the Si30xxPPT-EVB The S30xxPPT-EVB is used to interface the Si30xx chipset other audio system for easy evaluation. It uses an FPGA to translate the parallel port interface to the SSI bus to communicate to the ...
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Si30xxPPT-EVB Evaluation Software The Si30xxPPT-EVB includes an easy-to-use graphical interface for controlling the evaluation platform. This software allows the system designer to characterize the Si30xx DAA performance without constructing any custom hardware. The evaluation software includes the following features: ! ...
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Figure 1. Si30xxPPT-EVB Evaluation Software in the Audio Data Monitoring View Audio Data Monitoring View The audio data monitoring view is discussed in the following sections. Receive Audio Data of Channel# Allows selection of channel to control and view. The ...
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Si30xxPPT-EVB RX Control ! Monitor Mode: Allows the selection of several data modes. Digital Loopback mode routes the DAC data back to the receive path. On-hook mode configures the DAA to the on-hook mode. Off-hook mode configures the DAA to ...
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Figure 2. Si3056 System-Side Device Signal Flow Diagram Preliminary Rev. 1.0 Si30xxPPT-EVB 7 ...
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Si30xxPPT-EVB Figure 3. Si3021 System-Side Device Signal Flow Diagram Register Table Display View The DAA Register view allows the Si30xx DAA registers to be read or written. The user interface for the DAA Register view is shown in Figure 2 ...
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Advanced Configuration Advanced configuration of the application software is accomplished by using the “Configure DAA” selection in the “Configure” menu. The configuration panel is shown in Figure 4. The panel contents are detailed in the following list: ! FFT Window: ...
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Si30xxPPT-EVB Figure 5. Si30xx Signal Flow Diagram for the Si3056 Signal Flow Diagrams The signal flow diagrams of the Si30xx application software for the Si3056 device, shown in Figure 5 and Figure 6, assist users with programming DAA. Si30xx Signal ...
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Figure 6. Si30xx Signal Flow Diagram for Si3021 Signal Flow Diagrams The signal flow diagrams of the application software shown in Figure 6 assist users with programming DAA. Si30xx Signal Path Control ! TX Mute: Turns on/off the TXM bit ...
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Si30xxPPT-EVB Figure 7. Si3018/19 Line-side Device Signal Flow Diagram Line-Side Device Signal Path Control ! AL: Turns on/off AL bit on Register 2, bit 3. ! HBE: Turns on/off HBE bit on Register 2, bit 1. ! RXE: Turns on/off ...
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Figure 8. Si3012/14/15 Line Side Device Signal Flow Diagram Line-Side Device Signal Path Control ! AL: Turns on/off AL bit on Register 2, bit 3. ! HBE: Turns on/off HBE bit on Register 2, bit 1. ! RXE: Turns on/off ...
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Si30xxPPT-EVB Transhybrid Loss Calculation When “Transhybrid Loss Calculation” is selected, the Si3050PPT-EVB software will drive a signal with different frequencies and measure the transhybrid loss based on the following equation 20Log(TXpk-pk/ RXpk-pk). Frequencies used to measure this start ...
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Figure 10. Ringing Preliminary Rev. 1.0 Si30xxPPT-EVB Ringing ! RNGV-Enable: Turns on/off RNGV bit on Register 24, bit7 ! RAS[5:0]: Update RAS bits on Register 24 ! RMX[5:0]: Update RMX bits on Register 22 ! RCC[2:0]: Update RCC bits on ...
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VCC C50 Decou pling cap for C51 M0 RGDTb OFHKb MCLK MCLK OFHK R12 2 15 FSYNCb FSYNC RGDT/FSD/ SCLK SCLK SDO SDO GND ...
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Footprint of JP1 Top View Figure 12. Si3034/35/44 Daughter Card Schematic ( JP1 M0 ...
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Si30xxPPT-EVB Bill of Materials: Si3034-EVB Daughter Card Quantity Reference 2 C4, C6,C10,C16 2 C7, R4,C11,R21,C30 1 C12 1 C13 1 C14 2 C18,C19 1 C20 1 C22 1 C23 2 C24,C25 4 ...
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Bill of Materials: Si3035-EVB Daughter Card Quantity Reference 2 C4, C6,C10,C16 6 R3,C7,C8,C13,R25,R26 3 C9,C28,C29 1 C11 1 C12 7 R7,R8,C14,R15,R16,R17, R19 9 R12,R13,C18,C19,C20,C22, R24,R30,C30 1 C23 2 C24,C25 2 D1,D2 2 D3,D4 2 FB1,FB2 ...
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Si30xxPPT-EVB Bill of Materials: Si3044-EVB Daughter Card Quantity Reference 2 C4, C6,C10,C16 2 C7, R4,C11,R21,C30 1 C12 1 C13 1 C14 2 C18,C19 1 C20 1 C22 1 C23 2 C24,C25 4 ...
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Figure 1. Si3034/35/44 Daughter Card Silkscreen ...
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Figure 2. Si3034/35/44 Daughter Card Component Layer ...
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Figure 3. Si3034/35/44 Daughter Card Solder Layer ...
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VCC C50 Decou pling cap for C51 M0 RGDTb OFHKb MCLK MCLK OFHK R12 2 15 FSYNCb FSYNC RGDT/FSD/ SCLK SCLK SDO SDO GND ...
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Footprint of JP1 Top View Figure 14. Si3056 Daughter Card Schematic ( JP1 M0 ...
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Si30xxPPT-EVB Bill of Materials: Si3056-EVB Daughter Card Reference Value C2, 1.0 uF C6,C5 0 2.7 nF C9,C8 680 pF C10 0.01 uF C30,C31 DNP 120pF C51,C50 0 HD04 FB1,FB2 Ferrite ...
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Figure 15. Si3056 Daughter Card Silkscreen ...
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Figure 16. Si3056 Daughter Card Component Layer ...
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Figure 17. Si3056 Daughter Card Solder Layer ...
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Vio 2.2K 2. JP2 RGDT/FSD OFHKb MCLK 7 Vio 8 SCLK ...
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Vio pbRESETb SW1 100 C27 1uF SCLK SDO RESETb Vio R52 SCLK_IN 2.2K RESET_INb R53 10K Figure 19. Si30xx Motherboard Schematic ( C23 0.1 uF C24 R9 3 AOUT 7 0.1 uF ...
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RGDT/FSD OFHKb Board Config. mSel0 mSel1 M1 M0 MCLK SCLK Stand Alone GND GND GND Vio FSYNCb SDO Master w/ slaves Vio GND GND Vio FC/RGDT SDI GND Slave Vio Vio GND RESETb SCLK_IN FSD_OUT pbRESETb Vio RESET_INb JP10 JP9 ...
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Bill of Materials: Si30XX Motherboard Item Qty Reference C1,C2,C3,C4,C9,C10,C11 C12,C20,C21 C5,C6,C7,C8,C13,C14,C15 C16,C23,C24,C28,C29,C31, C32 C17 3 1 C18,C22 4 2 C19 5 1 C25 6 1 C26 7 1 C27 8 1 C30 9 1 D1,D2,D3,D4 10 ...
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Figure 21. Si30xx Motherboard Silkscreen ...
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Figure 22. Si30xx Motherboard Component Layer ...
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Figure 23. Si30xx Motherboard Solder Layer ...
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Notes: Si30xxPPT-EVB Preliminary Rev. 1.0 37 ...
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