KS8842-16MQL-EVAL Micrel Inc, KS8842-16MQL-EVAL Datasheet - Page 18

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KS8842-16MQL-EVAL

Manufacturer Part Number
KS8842-16MQL-EVAL
Description
EVAL KIT EXPERIMENTAL KS8842
Manufacturer
Micrel Inc
Datasheet

Specifications of KS8842-16MQL-EVAL

Main Purpose
Interface, Ethernet
Utilized Ic / Part
KS8842
Lead Free Status / RoHS Status
Not applicable / Not applicable
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Not Compliant
Ball Description for KSZ8842-16 Switches (8/16-Bit)
Micrel, Inc.
October 2007
Ball Number
D10
C10
A10
B10
E8
A9
B9
C9
D9
A8
RDYRTNN
Ball Name
SCAN_EN
TEST_EN
P1LED2
P1LED1
P1LED0
P2LED2
P2LED1
P2LED0
BCLK
Type
Opu
Opu
Opu
Opu
Opu
Opu
Ipd
Ipd
I
I
Ball Function
Test Enable
For normal operation, pull-down this ball to ground.
Scan Test Scan Mux Enable
For normal operation, pull-down this ball to ground.
Port 1 and Port 2 LED indicators
Notes:
1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;
Full Duplex = On (Full duplex); Off (Half duplex)
Speed = On (100BASE-T); Off (10BASE-T)
2. P1LED3 is ball A4. P2LED3 is ball C6.
Port 1 and Port 2 LED indicators
Note 3: RPT_COL = Blink; RPT_Link3/RX (Host port) = On/Blink;
RPT_Link2/RX (Port 2) = On/Blink; RPT_Link1/RX (Port 1) = On/Blink;
RPT_ACT = on if any activity, RPT_ERR3/2/1 = RX error on port 3, 2, or 1.
Ready Return Not:
For VLBus-like mode: Asserted by the host to complete synchronous read
cycles. If the host doesn’t connect to this ball, assert this ball.
For burst mode (32-bit interface only): Host drives this ball low to signal waiting
states.
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.
P1LED3
P1LED2/P2LED2
P1LED1/P2LED1
P1LED0/P2LED0
P1LED3
P1LED2/P2LED2
P1LED1/P2LED1
P1LED0/P2LED0
P1LED3, P2LED3
P1LED2, P2LED2
P1LED1, P2LED1
P1LED0, P2LED0
2
2
/P2LED3
/P2LED3
18
Switch Global Control Register 5: SGCR5 bit
[15,9]
[0,0] Default
RPT_COL, RPT_ACT
RPT_Link3/RX, RPT_ERR3
RPT_Link2/RX, RPT_ERR2
RPT_Link1/RX, RPT_ERR1
Switch Global Control Register 5:
SGCR5 bit [15,9]
[0,0] Default
Link/Act
Full duplex/Col
Speed
Reg. SGCR5 bit [15,9]
[1,0]
Act
Link
Full duplex/Col
Speed
1
3
defined as follows:
for Repeater mode defined as follows:
KSZ8842-16/32 MQL/MVL/MVLI/MBL
[0,1]
100Link/Act
10Link/Act
Full duplex
[1,1]
[0,1] [1,0] [1,1]
M9999-102207-1.9

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