KS8842-16MQL-EVAL Micrel Inc, KS8842-16MQL-EVAL Datasheet
KS8842-16MQL-EVAL
Specifications of KS8842-16MQL-EVAL
Related parts for KS8842-16MQL-EVAL
KS8842-16MQL-EVAL Summary of contents
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General Description The KSZ8842-series of 2-port switches includes PCI and non-PCI CPU interfaces, and are available in 8/16-bit and 32-bit bus designs (see Ordering This datasheet describes the KSZ8842M-series of non- PCI CPU interface chips. For information on the KSZ8842 ...
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Micrel, Inc. Features Switch Management • Non-blocking switch fabric assures fast packet delivery by utilizing a 1K entry forwarding table • Fully compliant with IEEE 802.3u standards • Full-duplex IEEE 802.3x flow control (Pause) with force mode option • Half-duplex ...
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Micrel, Inc. Ordering Information Part Number KSZ8842-16MQL KSZ8842-32MQL KSZ8842-16MVL KSZ8842-32MVL KSZ8842-16MVLI KSZ8842-32MVLI KSZ8842-16MBL KSZ8842-16MBLI KSZ8842-16MQL-Eval KSZ8842-16MBL-Eval Revision History Revision Date 1.0 06/30/05 1.1 07/19/05 1.2 08/08/05 1.3 10/04/05 1.4 11/01/05 1.5 03/20/06 1.6 11/30/06 1.7 05/24/07 1.8 08/09/07 1.9 10/22/07 ...
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Micrel, Inc. Content Pin Configuration for KSZ8842-16 Switches (8/16-Bit) ...................................................................................... 11 Ball Configuration for KSZ8842-16 Switches (8/16-Bit) ..................................................................................... 12 Pin Description for KSZ8842-16 Switches (8/16-Bit) .......................................................................................... 13 Ball Description for KSZ8842-16 Switches (8/16-Bit) ......................................................................................... 18 Pin Configuration for KSZ8842-32 Switches ...
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Micrel, Inc. “Multicast Address Insertion” in the Static MAC Table ......................................................................................................45 IPv6 MLD Snooping...............................................................................................................................................................45 Port Mirroring Support ...........................................................................................................................................................45 IEEE 802.1Q VLAN Support..................................................................................................................................................45 QoS Priority Support..............................................................................................................................................................46 Port-Based Priority.................................................................................................................................................................46 802.1p-Based Priority ............................................................................................................................................................46 DiffServ based Priority ...........................................................................................................................................................47 Rate Limiting Support ............................................................................................................................................................47 MAC Filtering ...
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Micrel, Inc. Bank 19 Multicast Table Register 3 (0x06): MTR3 ................................................................................................................73 Banks 20 – 31: Reserved ......................................................................................................................................................73 Bank 32 Switch ID and Enable Register (0x00): SIDER ........................................................................................................73 Bank 32 Switch Global Control Register 1 (0x02): SGCR1 ...................................................................................................73 Bank 32 Switch ...
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Micrel, Inc. Bank 48 Port 1 VID Control Register (0x04): P1VIDCR.......................................................................................................101 Bank 48 Port 1 Control Register 3 (0x06): P1CR3 ..............................................................................................................101 Bank 48 Port 1 Ingress Rate Control Register (0x08): P1IRCR...........................................................................................102 Bank 48 Port 1 Egress Rate Control Register (0x0A): ...
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Micrel, Inc. Appendix .............................................................................................................................................................. 141 October 2007 KSZ8842-16/32 MQL/MVL/MVLI/MBL 8 M9999-102207-1.9 ...
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Micrel, Inc. List of Figures Figure 1. KSZ8842M Functional Diagram ..................................................................................................................................... 1 Figure 2. Standard – KSZ8842-16 MQL 128-Pin PQFP (Top View)............................................................................................ 11 Figure 3. Option – KSZ8842-16 MVL 128-Pin LQFP (Top View) ................................................................................................ 11 Figure 4. KSZ8842-16MBL 100-Ball LFBGA ...
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Micrel, Inc. List of Tables Table 1. MDI/MDI-X Pin Definitions............................................................................................................................................. 29 Table 2. Bus Interface Unit Signal Grouping ............................................................................................................................... 38 Table 3: Transmit Queue Frame Format ..................................................................................................................................... 41 Table 4. Transmit Control Word Bit Fields................................................................................................................................... 42 Table 5. Transmit Byte ...
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Micrel, Inc. Pin Configuration for KSZ8842-16 Switches (8/16-Bit ...
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Micrel, Inc. Ball Configuration for KSZ8842-16 Switches (8/16-Bit) October 2007 Figure 4. KSZ8842-16MBL 100-Ball LFBGA (Top View) 12 KSZ8842-16/32 MQL/MVL/MVLI/MBL M9999-102207-1.9 ...
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Micrel, Inc. Pin Description for KSZ8842-16 Switches (8/16-Bit) Pin Number Pin Name Type 1 TEST_EN 2 SCAN_EN 3 P1LED2 Opu 4 P1LED1 Opu 5 P1LED0 Opu 6 P2LED2 Opu 7 P2LED1 Opu 8 P2LED0 Opu 9 DGND Gnd 10 VDDIO ...
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Micrel, Inc. Pin Number Pin Name Type 12 BCLK Ipd 13 NC Ipu 14 NC Opu 15 SRDYN Opu 16 INTRN Opd 17 LDEVN Opd 18 RDN Ipd 19 EECS Opu 20 ARDY Opd 21 CYCLEN Ipd 22 P2LED3 Opd ...
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Micrel, Inc. Pin Number Pin Name Type 27 P1LED3 Opd 28 EEDO Opd 29 EESK Opd 30 EEDI Ipd 31 SWR Ipd 32 AEN Ipu 33 WRN Ipd 34 DGND Gnd 35 ADSN Ipd 36 PWRDN Ipu 37 AGND Gnd ...
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Micrel, Inc. Pin Number Pin Name Type 55 TXM2 I/O 56 TXP2 I/O 57 VDDA P 58 AGND Gnd 59 NC Ipu 60 NC Ipu 61 ISET O 62 AGND Gnd 63 VDDAP P 64 AGND Gnd ...
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Micrel, Inc. Pin Number Pin Name Type 92 VDDIO 100 NC I 101 NC I 102 NC I ...
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Micrel, Inc. Ball Description for KSZ8842-16 Switches (8/16-Bit) Ball Number Ball Name Type E8 TEST_EN D10 SCAN_EN A10 P1LED2 Opu B10 P1LED1 Opu C10 P1LED0 Opu A9 P2LED2 Opu B9 P2LED1 Opu C9 P2LED0 Opu D9 RDYRTNN Ipd A8 BCLK ...
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Micrel, Inc. Ball Number Ball Name Type B8 SRDYN Opu C8 INTRN Opd A7 LDEVN Opd B7 RDN Ipd C7 EECS Opu A6 ARDY Opd B6 CYCLEN Ipd C6 P2LED3 Opd A5 VLBUSN Ipd B5 EEEN Ipd A4 P1LED3 Opd ...
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Micrel, Inc. Ball Number Ball Name Type C3 SWR Ipd A2 AEN Ipu B2 WRN Ipd A1 ADSN Ipd B1 PWRDN Ipu C1 RXP1 I/O C2 RXM1 I/O D1 TXP1 I/O D2 TXM1 I/O F2 RXM2 I/O F1 RXP2 I/O ...
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Micrel, Inc. Ball Number Ball Name Type BE1N I K8 BE0N I K9 D15 I/O K10 D14 I/O J9 D13 I/O J10 D12 I/O J8 D11 I/O H9 D10 I/O H10 D9 I I/O ...
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Micrel, Inc. Pin Configuration for KSZ8842-32 Switches (32-Bit ...
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Micrel, Inc. Pin Description for KSZ8842-32 Switches (32-Bit) Pin Number Pin Name Type 1 TEST_EN 2 SCAN_EN 3 P1LED2 Opu 4 P1LED1 Opu 5 P1LED0 Opu 6 P2LED2 Opu 7 P2LED1 Opu 8 P2LED0 Opu 9 DGND Gnd 10 VDDIO ...
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Micrel, Inc. Pin Number Pin Name Type 12 BCLK Ipd 13 DATACSN Ipu 14 NC Opu 15 SRDYN Opu 16 INTRN Opd 17 LDEVN Opd 18 RDN Ipd 19 EECS Opu 20 ARDY Opd 21 CYCLEN Ipd 22 P2LED3 Opd ...
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Micrel, Inc. Pin Number Pin Name Type 26 EEEN Ipd 27 P1LED3 Opd 28 EEDO Opd 29 EESK Opd 30 EEDI Ipd 31 SWR Ipd 32 AEN Ipu 33 WRN Ipd 34 DGND Gnd 35 ADSN Ipd 36 PWRDN Ipu ...
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Micrel, Inc. Pin Number Pin Name Type 54 AGND Gnd 55 TXM2 I/O 56 TXP2 I/O 57 VDDA P 58 AGND Gnd 59 NC Ipu 60 NC Ipu 61 ISET O 62 AGND Gnd 63 VDDAP P 64 AGND Gnd ...
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Micrel, Inc. Pin Number Pin Name Type 92 VDDIO P 93 D30 I/O 94 D29 I/O 95 D28 I/O 96 D27 I/O 97 D26 I/O 98 D25 I/O 99 D24 I/O 100 D23 I/O 101 D22 I/O 102 D21 I/O ...
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Micrel, Inc. Functional Description The KSZ8842M contains two 10/100 physical layer transceivers (PHYs), two MAC units, and a DMA channel integrated with a Layer-2 switch. The KSZ8842M contains a bus interface unit (BIU), which controls the KSZ8842M via an 8, ...
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Micrel, Inc. Power Management The KSZ8842M features per port power-down mode. To save power, the user can power-down the port that is not in use by setting bit 11 in either P1CR4 or P1MBCR register for port 1 and setting ...
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Micrel, Inc. Crossover Cable A crossover cable connects an MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). ...
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Micrel, Inc. Start Auto Negotiation Force Link Setting YES Bypass Auto Negotiation and Set Link Mode LinkMD Cable Diagnostics The KSZ8842M LinkMD uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, ...
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Micrel, Inc. Usage LinkMD can be run at any time by making sure Auto MDIX has been disabled. To disable Auto-MDIX, write a ‘1’ to P1CR4[10] for port 1 or P2CR4[10] for port 2 to enable manual control over the ...
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Micrel, Inc. Forwarding The KSZ8842M forwards packets using the algorithm that is depicted in the following flowcharts. Figure 10 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table ...
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Micrel, Inc. Figure 11. Destination Address Resolution Flow Chart in Stage Two The KSZ8842M will not forward the following packets: 1. Error packets. These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. ...
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Micrel, Inc. Switching Engine The KSZ8842M features a high-performance switching engine to move data to and from the MAC’s packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The switching engine has ...
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Micrel, Inc. To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8842M discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other stations ...
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Micrel, Inc. physical data bus. For example, for a 32-bit system/host data bus, it allows 8, 16, and 32-bit data transfers (KSZ8842- 32MQL); for a 16-bit system/host data bus, it allows 8 and 16-bit data transfers (KSZ8842-16MQL); and for 8-bit ...
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Micrel, Inc. (1) Signal Type CYCLEN I SWR I SRDYN O RDYRTNN I BCLK I Asynchronous Transfer Signals RDN I WRN I ARDY O Note Input Output. I/O = Bi-directional. Regardless of whether the transfer ...
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Micrel, Inc. BE2N, BE1N, and BE0N are ignored as shown in the Figure 19. No other registers can be accessed by asserting DATACSN. The data transfer is the same as in the first case. Independent of the type of asynchronous ...
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Micrel, Inc. ISA Non-burst EISA Burst VLBus Figure 12. Mapping from ISA-like, EISA-like, and VLBus-like transactions to the KSZ8842M Bus KSZ8842-16 HA[1] A[1] HA[15:2] A[15:2] HD[7:0] D[7:0] D[15:8] HA[0] BE0N BE1N VDD 8-bit Data Bus Figure 13. KSZ8842M 8-Bit, 16-Bit, ...
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Micrel, Inc. BIU Implementation Principles Since the KSZ8842M is an I/O device with 16 addressable locations, address decoding is based on the values of A15-A4 and AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer ...
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Micrel, Inc. Bit Description 15 TXIC Transmit Interrupt on Completion When bit is set, the KSZ8842M sets the transmit interrupt after the present frame has been transmitted. 14-10 Reserved TXDPN Transmit Destination Port Number 9-8 When bit is set, this ...
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Micrel, Inc. Bit Description 15 RXFV Receive Frame Valid When bit is set, indicates that the present frame in the receive packet memory is valid and received from MAC/PHY. The status information currently in this location is also valid. When ...
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Micrel, Inc. Advanced Switch Functions Spanning Tree Support To support spanning tree, the host port is the designated port for the processor. The other ports can be configured in one of the five spanning tree states via “transmit enable”, “receive ...
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Micrel, Inc. IGMP Support For Internet Group Management Protocol (IGMP) support in Layer 2, the KSZ8842M provides two components: “IGMP” Snooping The KSZ8842M traps IGMP packets and forwards them only to the processor (host port). The IGMP packets are identified ...
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Micrel, Inc. DA found in Static MAC Use FID flag? Table? No Don’t care No Don’t care Yes 0 Yes 1 Yes 1 Yes 1 FID+SA found in Dynamic MAC Table? No Yes QoS Priority Support The KSZ8842M provides Quality ...
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Micrel, Inc. Bytes Preamble DA Bits Tagged Packet Type 802.1q VLAN Tag (8100 for Ethernet) 802.1p based priority is enabled by bit 5 of registers P1CR1, P2CR1, and P3CR1 for ports 1, 2, and the host port, ...
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Micrel, Inc. For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic. Inter frame gap is stretched on a per frame base to generate smooth, non-burst egress traffic. The throughput of ...
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Micrel, Inc. The format for ConfigParam is shown in Table 13. Bit Bit Name Description 15 -2 Reserved Reserved Internal clock rate selection 1 Clock_Rate 0: 125 MHz 1: 25 MHz Note: At power up, this chip operates on 125 ...
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Micrel, Inc Figure 16. Port 1 and port 2 Near-End (Remote) Loopback Path October 2007 ...
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Micrel, Inc. CPU Interface I/O Registers The KSZ8842M provides an EISA-like, ISA-like, or VLBUS-like bus interface for the CPU to access its internal I/O registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. ...
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Micrel, Inc. Internal I/O Space Mapping I/O Register Location 32-Bit 16-Bit 8-Bit Bank 0 Base 0x0 Address 0x0 [7:0] - 0x1 Base 0x1 Address 0x0 [15:8] To 0x3 0x2 0x2 Reserved - 0x3 0x3 QMU RX Flow Control 0x4 Watermark ...
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Micrel, Inc. Internal I/O Space Mapping (continued) I/O Register Location 32-Bit 16-Bit 8-Bit Bank 8 0x0 0x0 - 0x1 0x1 0x0 To 0x3 0x2 0x2 - 0x3 0x3 0x4 0x4 - 0x5 0x5 0x4 To 0x7 0x6 0x6 - 0x7 ...
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Micrel, Inc. Internal I/O Space Mapping (continued) I/O Register Location 32-Bit 16-Bit 8-Bit Bank 16 Transmit 0x0 Control 0x0 [7:0] - 0x1 Transmit 0x1 Control 0x0 [15:8] To Transmit 0x3 0x2 Status 0x2 [7:0] - 0x3 Transmit 0x3 Status [15:8] ...
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Micrel, Inc. Internal I/O Space Mapping (continued) I/O Register Location 32-Bit 16-Bit 8-Bit Bank 24 0x0 0x0 - 0x1 0x1 0x0 To 0x3 0x2 0x2 - 0x3 0x3 0x4 0x4 - 0x5 0x5 0x4 To 0x7 0x6 0x6 - 0x7 ...
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Micrel, Inc. Internal I/O Space Mapping (continued) I/O Register Location 32-Bit 16-Bit 8-Bit Bank 32 Switch ID and 0x0 Enable 0x0 [7:0] - 0x1 Switch ID and 0x1 Enable 0x0 [15:8] To Switch Global 0x3 0x2 Control 1 0x2 [7:0] ...
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Micrel, Inc. Internal I/O Space Mapping (continued) I/O Register Location 32-Bit 16-Bit 8-Bit Bank 40 TOS Priority Control 1 0x0 [7:0] 0x0 - 0x1 TOS Priority Control 1 0x1 0x0 [15:8] To TOS Priority 0x3 Control 2 0x2 [7:0] 0x2 ...
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Micrel, Inc. Internal I/O Space Mapping (continued) I/O Register Location 32-Bit 16-Bit 8-Bit Bank 48 Port 1 Control 1 0x0 [7:0] 0x0 - 0x1 Port 1 Control 1 0x1 0x0 [15:8] To 0x3 Port 1 0x2 Control 2 0x2 [7:0] ...
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Micrel, Inc. Internal I/O Space Mapping (continued) I/O Register Location 32-Bit 16-Bit 8-Bit Bank 56 0x0 0x0 - 0x1 0x1 0x0 To 0x3 0x2 0x2 - 0x3 0x3 0x4 0x4 - 0x5 0x5 0x4 To 0x7 0x6 0x6 - 0x7 ...
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Micrel, Inc. Register Map: Switch & MAC/PHY Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes unpredictable and often fatal results. If the user wants to write to these reserved bits, ...
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Micrel, Inc. Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR This register contains the user defined QMU RX Queue high watermark configuration bit as below. Bit Default Value R/W 15-13 0x0 11-0 ...
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Micrel, Inc. Bank 1: Reserved Except Bank Select Register (0xE). Bank 2 Host MAC Address Register Low (0x00): MARL This register along with the other two Host MAC address registers are loaded starting at word location 0x1 of the EEPROM ...
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Micrel, Inc. Bank 3 On-Chip Bus Control Register (0x00): OBCR This register controls the on-chip bus speed for the KSZ8842M used for power management when the external host CPU is running at a slow frequency. The default of ...
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Micrel, Inc. Bank 3 Memory BIST INFO Register (0x04): MBIR Bit Default Value R/W 15-13 0x0 10 2 Bank 3 Global Reset Register ...
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Micrel, Inc. Bank 16 Transmit Control Register (0x00): TXCR This register holds control information programmed by the CPU to control the QMU transmit module function. Bit Default Value R 0x0 RW 13 0x0 RW 12-4 - ...
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Micrel, Inc. Bit Default Value R/W 6 0x0 RW 5 0x0 RW 4 0x0 RW 3 0x0 RW 2 0x0 0x0 RW Bank 16 TXQ Memory Information Register (0x08): TXMIR This register indicates the amount ...
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Micrel, Inc. Bank 17 TXQ Command Register (0x00): TXQCR This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in the TXQ memory is queued for transmit. Bit Default Value ...
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Micrel, Inc. Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment is set, it will automatically increment the RXQ Pointer ...
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Micrel, Inc. Bank 18 Interrupt Enable Register (0x00): IER This register enables the interrupts from the QMU and other sources. Bit Default Value R/W 15 0x0 RW 14 0x0 RW 13 0x0 RW 12 0x0 RW 11 0x0 RW 10 ...
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Micrel, Inc. Bank 18 Interrupt Status Register (0x02): ISR This register contains the status bits for all QMU and other interrupt sources. When the corresponding enable bit is set, it causes the interrupt pin to be asserted. This register is ...
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Micrel, Inc. Bank 18 Receive Status Register (0x04): RXSR This register indicates the status of the current received frame and mirrors the Receive Status word of the Receive Frame in the RXQ. Bit Default Value R 14-10 ...
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Micrel, Inc. Bank 18 Receive Byte Counter Register (0x06): RXBC This register indicates the status of the current received frame and mirrors the Receive Byte Count word of the Receive Frame in the RXQ. Bit Default Value R/W 15-11 - ...
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Micrel, Inc. Bank 19 Multicast Table Register 3 (0x06): MTR3 Multicast table register 3. Bit Default Value R/W 15-0 0x0000 RW Banks 20 – 31: Reserved Except Bank Select Register (0xE). Bank 32 Switch ID and Enable Register (0x00): SIDER ...
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Micrel, Inc. Bit Default R 7 0x0 RW 2 Bank 32 Switch Global Control Register 2 (0x04): SGCR2 This register contains the global ...
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Micrel, Inc. Bit Default R October 2007 Description Unicast Port-VLAN Mismatch Discard packets ...
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Micrel, Inc. Bank 32 Switch Global Control Register 3 (0x06): SGCR3 This register contains the global control for the switch function. Bit Default R/W 15-8 0x63 ...
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Micrel, Inc. Bank 32 Switch Global Control Register 5 (0x0A): SGCR5 This register contains the global control for the switch function. Bit Default R 14-12 0x0 RW 11-10 0x2 7-0 ...
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Micrel, Inc. Bank 33 Switch Global Control Register 6 (0x00): SGCR6 Bit Default R/W 15-14 0x3 R/W 13-12 0x3 R/W 11-10 0x2 R/W 9-8 0x2 R/W 7-6 0x1 R/W 5-4 0x1 R/W 3-2 0x0 R/W 1-0 0x0 R/W Bank 33 ...
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Micrel, Inc. Bank 39 MAC Address Register 2 (0x02): MACAR2 This register contains the MAC address for the switch function. This MAC address is used for sending PAUSE frame. Bit Default R/W 15-0 0xA1FF RW Bank 39 MAC Address Register ...
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Micrel, Inc. Bank 40 TOS Priority Control Register 2 (0x02): TOSR2 This register contains the TOS priority control for the switch function. Bit Default R/W 15- 13-12 0 R/W 11-10 0 R/W 9-8 0 R/W 7-6 0 R/W ...
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Micrel, Inc. Bank 40 TOS Priority Control Register 3 (0x04): TOSR3 This register contains the TOS priority control for the switch function. Bit Default R/W 15- 13-12 0 R/W 11-10 0 R/W 9-8 0 R/W 7-6 0 R/W ...
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Micrel, Inc. Bank 40 TOS Priority Control Register 4 (0x06): TOSR4 This register contains the TOS priority control for the switch function. Bit Default R/W 15- 13-12 0 R/W 11-10 0 R/W 9-8 0 R/W 7-6 0 R/W ...
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Micrel, Inc. Bank 40 TOS Priority Control Register 5 (0x08): TOSR5 This register contains the TOS priority control for the switch function. Bit Default R/W 15- 13-12 0 R/W 11-10 0 R/W 9-8 0 R/W 7-6 0 R/W ...
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Micrel, Inc. Bank 40 TOS Priority Control Register 6 (0x0A): TOSR6 This register contains the TOS priority control for the switch function. Bit Default R/W 15- 13-12 0 R/W 11-10 0 R/W 9-8 0 R/W 7-6 0 R/W ...
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Micrel, Inc. Bank 41 TOS Priority Control Register 7 (0x00): TOSR7 This register contains the TOS priority control for the switch function. Bit Default R/W 15- 13-12 0 R/W 11-10 0 R/W 9-8 0 R/W 7-6 0 R/W ...
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Micrel, Inc. Bank 41 TOS Priority Control Register 8 (0x02): TOSR8 This register contains the TOS priority control for the switch function. Bit Default R/W 15- 13-12 0 R/W 11-10 0 R/W 9-8 0 R/W 7-6 0 R/W ...
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Micrel, Inc. Bank 42 Indirect Access Data Register 1 (0x02): IADR1 This register contains the indirect data for the switch function. Bit Default R/W 15-8 0x00 6-3 0x0 RO 2-0 0x0 RO Bank 42 Indirect Access ...
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Micrel, Inc. Bank 44 Digital Testing Status Register (0x00): DTSR This register contains the user defined register for the switch function. Bit Default R/W 15-3 0x0000 RO 2-0 0x0 RO Bank 44 Analog Testing Status Register (0x02): ATSR This register ...
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Micrel, Inc. Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR This register contains Media Independent Interface (MII) register for switch port 1 as defined in the IEEE 802.3 specification. Bit Default R ...
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Micrel, Inc. Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR This register contains the MII register status for the switch port 1 function. Bit Default R ...
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Micrel, Inc. Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR This register contains the PHY ID (low) for the switch port 1 function. Bit Default R/W 15-0 0x1430 RO Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR This ...
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Micrel, Inc. Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0x0A): P1ANLPR This register contains the auto-negotiation link partner ability for the switch port 1 function. Bit Default R 12-11 ...
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Micrel, Inc. Bit Default R/W Description Power Down power down normal operation Isolate Not supported Restart restart auto-negotiation normal operation, Force Full ...
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Micrel, Inc. Bank 46 PHY 2 MII-Register Basic Status Register (0x02): P2MBSR This register contains the MII register for the switch port 2 function. Bit Default R ...
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Micrel, Inc. Bank 46 PHY 2 PHYID High Register (0x06): PHY2IHR This register contains the PHY ID (high) for the switch port 2 function. Bit Default R/W 15-0 0x0022 RO Bank 46 PHY 2 Auto-Negotiation Advertisement Register (0x08): P2ANAR This ...
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Micrel, Inc. Bank 46 PHY 2 Auto-Negotiation Link Partner Ability Register (0x0A): P2ANLPR This register contains the auto-negotiation link partner ability for the switch port 2 function. Bit Default R 12-11 ...
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Micrel, Inc. Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL This register contains the control and status information of PHY1. Bit Default R/W 15-6 0x000 ...
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Micrel, Inc. Bank 47 PHY2 Special Control/Status Register (0x06): P2PHYCTRL This register contains the control and status information of PHY2. Bit Default R/W 15-6 0x000 ...
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Micrel, Inc. Bank 48 Port 1 Control Register 1 (0x00): P1CR1 This register contains the global per port control for the switch function. Bit Default R/W 15-8 0x00 4-3 0x0 ...
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Micrel, Inc. Bank 48 Port 1 Control Register 2 (0x02): P1CR2 This register contains the global per port control for the switch function. Bit Default R ...
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Micrel, Inc. Bank 48 Port 1 VID Control Register (0x04): P1VIDCR This register contains the global per port control for the switch function. Bit Default R/W 15-13 0x0 11-0 0x001 RW Note: This VID Control register ...
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Micrel, Inc. Bank 48 Port 1 Ingress Rate Control Register (0x08): P1IRCR Bit Default R/W 15-12 0x0 RW 11-8 0x0 RW October 2007 Description Ingress Pri3 Rate Priority 3 frames will be discarded after the ingress rate selected as shown ...
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Micrel, Inc. Bit Default R/W 7-4 0x0 RW 3-0 0x0 RW October 2007 Description Ingress Pri1 Rate Priority 1 frames will be discarded after the ingress rate selected as shown below is reached or exceeded. 0000 = Not limited (default) ...
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Micrel, Inc. Bank 48 Port 1 Egress Rate Control Register (0x0A): P1ERCR Bit Default R/W 15-12 0x0 RW 11-8 0x0 RW October 2007 Description Egress Pri3 Rate Egress data rate limit for priority 3 frames. Output traffic from this priority ...
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Micrel, Inc. Bit Default R/W 7-4 0x0 RW 3-0 0x0 RW October 2007 Description Egress Pri1 Rate Egress data rate limit for priority 1 frames. Output traffic from this priority queue is shaped according to the egress rate selected below: ...
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Micrel, Inc. Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD Bit Default R/W Description Vct_10m_short 1 = Less than 10 meter short. 14-13 0x0 RO Vct_result VCT result. [00] = normal condition. [01] = open ...
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Micrel, Inc. Bank 49 Port 1 Control Register 4 (0x02): P1CR4 This register contains the global per port control for the switch function. Bit Default R/W Description LED Off 1 = Turn off all of the port ...
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Micrel, Inc. Bit Default R/W Description Advertised 100BT full-duplex capability advertise 100BT full-duplex capability suppress 100BT full-duplex capability from transmission to link partner. Advertised 100BT half-duplex capability advertise ...
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Micrel, Inc. Bit Default R/W Description AN Done done not done Link Good 1 = link good link not good Partner flow control ...
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Micrel, Inc. Bank 51 Port 2 PHY Special Control/Status, LinkMD (0x00): P2SCSLMD Bit Default R/W Description Vct_10m_short 1 = Less than 10 meter short. 14-13 0x0 RO Vct_result VCT result. [00] = normal condition. [01] = open ...
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Micrel, Inc. Bank 51 Port 2 Control Register 4 (0x02): P2CR4 This register contains the global per port control for the switch function. Bit Default R/W Description LED Off 1 = turn off all of the port ...
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Micrel, Inc. Bit Default R/W Description Advertised 100BT Full-duplex capability advertise 100BT full-duplex capability suppress 100BT full-duplex capability from transmission to the link partner. Advertised 100BT half-duplex capability ...
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Micrel, Inc. Bank 51 Port 2 Status Register (0x04): P2SR This register contains the global per port status for the switch function. Bit Default R/W Description HP_mdix Auto MDI-X mode Micrel Auto ...
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Micrel, Inc. Bank 52 Host Port Control Register 1 (0x00): P3CR1 This register contains the global per port control for the switch function. See description in P1CR1, Bank 48 (0x00). Bank 52 Host Port Control Register 2 (0x02): P3CR2 This ...
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Micrel, Inc. Bank 52 Host Port VID Control Register (0x04): P3VIDCR This register contains the global per port control for the switch function. See description in P1VIDCR, Bank 48 (0x04) Bank 52 Host Port Control Register 3 (0x06): P3CR3 This ...
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Micrel, Inc. MIB (Management Information Base) Counters The KSZ8842M provides 34 MIB counters for each port. These counters are used to monitor the port activity for network management. The MIB counters are formatted “per port” as shown in Table 14 ...
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Micrel, Inc. Offset Counter Name 0x13 Rx1024to1522Octets 0x14 TxLoPriorityByte 0x15 TxHiPriorityByte 0x16 TxLateCollision 0x17 TxPausePkts 0x18 TxBroadcastPkts 0x19 TxMulticastPkts 0x1A TxUnicastPkts 0x1B TxDeferred 0x1C TxTotalCollision 0x1D TxExcessiveCollision 0x1E TxSingleCollision 0x1F TxMultipleCollision Format of “All Ports Dropped Packet” MIB Counters Bit ...
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Micrel, Inc. Examples: 1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E) Write to reg. IACR with 0x1c0e (set indirect address and trigger a read MIB counters operation) Then Read reg. IADR5 (MIB counter value ...
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Micrel, Inc. Static MAC Address Table The KSZ8842M supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look up, The KSZ8842M searches both tables to make a packet forwarding decision. In response ...
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Micrel, Inc. Dynamic MAC Address Table The Dynamic MAC address is a read only table. Bit Default Value R 70- 65-56 0x000 RO 55-54 RO 53- 51-48 0x0 RO 0x0000_0000_ 47-0 RO ...
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Micrel, Inc. VLAN Table The KSZ8842M uses the VLAN table to perform look-ups. If 802.1Q VLAN mode is enabled (SGCR2[15]), this table will be used to retrieve the VLAN information that is associated with the ingress packet. This information includes ...
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Micrel, Inc. Absolute Maximum Ratings Description Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering, 10 sec) Storage Temperature (Ts) Note: Exceeding the absolute maximum rating may damage the device. Stresses greater than those listed in the table above may ...
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Micrel, Inc. Electrical Characteristics Parameter Supply Current for 100BASE-TX Operation 100BASE-TX (analog core + PLL + digital core + transceiver + digital I/O) Supply Current for 10BASE-T Operation 10BASE-T (analog core + PLL + digital core + transceiver + digital ...
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Micrel, Inc. Timing Specifications Asynchronous Timing without using Address Strobe (ADSN = 0) Addr, AEN, BExN ADSN Read Data RDN, WRN Write Data ARDY (Read Cycle) ARDY ( Write Cycle) Symbol Parameter t1 A1-A15, AEN, BExN[3:0] valid to RDN, WRN ...
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Micrel, Inc. Asynchronous Timing using Address Strobe (ADSN) Addr, AEN, BExN ADSN Read Data RDN, WRN Write Data ARDY (Read Cycle) ARDY ( Write Cycle) Symbol Parameter t1 A1-A15, AEN, BExN[3:0] valid to RDN, WRN active t2 Read data valid ...
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Micrel, Inc. Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL device only) DATACSN Read Data RDN, WRN Write Data ARDY (Read Cycle) ARDY ( Write Cycle) Symbol Parameter t1 DATACSN setup to RDN, WRN active t2 DATACSN hold after RDN, WRN inactive (assume ...
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Micrel, Inc. Address Latching Timing for All Modes ADSN Address, AEN, BExN LDEVN Symbol Parameter t1 A1-A15, AEN, BExN[3:0] setup to ADSN t2 A1-A15, AEN, BExN[3:0] hold after ADSN rising t3 A4-A15, AEN to LDEVN delay October 2007 t1 t3 ...
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Micrel, Inc. Synchronous Timing in Burst Write (VLBUSN = 1) Symbol Parameter t1 SWR setup to BCLK falling t2 DATDCSN setup to BCLK rising t3 CYCLEN setup to BCLK rising t4 Write data setup to BCLK rising t5 Write data ...
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Micrel, Inc. Synchronous Timing in Burst Read (VLBUSN = 1) BCLK DATACSN t1 SWR CYCLEN Read Data RDYRTNN SRDYN Symbol Parameter t1 SWR setup to BCLK falling t2 DATDCSN setup to BCLK rising t3 CYCLEN setup to BCLK rising t4 ...
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Micrel, Inc. Synchronous Write Timing (VLBUSN = 0) BCLK Address, AEN, BExN ADSN SWR CYCLEN Write Data SRDYN RDYRTNN Symbol Parameter t1 A1-A15, AEN, BExN[3:0] setup to ADSN rising t2 A1-A15, AEN, BExN[3:0] hold after ADSN rising t3 CYCLEN setup ...
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Micrel, Inc. Synchronous Read Timing (VLBUSN = 0) BCLK Address, AEN, BExN ADSN SWR CYCLEN Read Data SRDYN RDYRTNN Symbol Parameter t1 A1-A15, AEN, BExN[3:0] setup to ADSN rising t2 A1-A15, AEN, BExN[3:0] hold after ADSN rising t3 CYCLEN setup ...
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Micrel, Inc. EEPROM Timing EECS *1 1 EESK EEDO 11 High-Z EEDI *1 Start bit Timing Description Parameter tcyc Clock cycle ts Setup time th Hold time October 2007 D15 Figure 25. EEPROM Read Cycle Timing Diagram ...
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Micrel, Inc. Auto Negotiation Timing Timing Description Parameter t FLP burst to FLP BTB burst t FLP burst width FLPW t Clock/Data pulse PW width t Clock pulse to CTD data pulse t Clock pulse to CTC clock pulse Number ...
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Micrel, Inc. Reset Timing As long as the stable supply voltages to reset High timing (minimum of 10ms) are met, there is no power-sequencing requirement for the KSZ8842M supply voltage (3.3V). The reset timing requirement is summarized in the Figure ...
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Micrel, Inc. Selection of Isolation Transformers A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended to exceed FCC requirements. Table 35 gives recommended transformer characteristics. Parameter Turns ratio Open-circuit inductance ...
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Micrel, Inc. Package Information October 2007 Figure 28. 128-Pin PQFP Package. 136 KSZ8842-16/32 MQL/MVL/MVLI/MBL M9999-102207-1.9 ...
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Micrel, Inc. October 2007 Figure 29. Optional 128-Pin LQFP Package 137 KSZ8842-16/32 MQL/MVL/MVLI/MBL M9999-102207-1.9 ...
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Micrel, Inc. October 2007 Figure 30. Optional 100-Ball LFBGA Package 138 KSZ8842-16/32 MQL/MVL/MVLI/MBL M9999-102207-1.9 ...
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Micrel, Inc. Acronyms and Glossary BIU Bus Interface Unit BPDU Bridge Protocol Data Unit CMOS Complementary Metal Oxide Semiconductor CRC Cyclic Redundancy Check Cut-through switch DA Destination Address DMA Direct Memory Access EEPROM Electronically Erasable Programmable Read-only Memory EISA Extended ...
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Micrel, Inc. MDI Medium Dependent Interface MDI-X Medium Dependent Interface Crossover MIB Management Information Base MII Media Independent Interface NIC Network Interface Card NPVID Non Port VLAN ID PLL Phase-Locked Loop PME Power Management Event QMU Queue Management Unit SA ...
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Micrel, Inc. Appendix The 1.2V LDO output (pin 24) sometimes unable reaches to 1.2V level and stay at <0.6V due to high temperature (>50°C) or 3.3V supply ramps up too slow. We recommend that by adding a 100-ohm resistor between ...