ISD-ES511 Nuvoton Technology Corporation of America, ISD-ES511 Datasheet - Page 49

• Manufacturer Part Number: ISD-ES511
• Description: EVALUATION SYSTEM FOR ISD5100
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ChipCorder®r

Specifications of ISD-ES511

• Main Purpose: Audio, Voice Record/Playback
• Utilized Ic / Part: ISD5102, ISD5104, ISD5108, ISD5116
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

(Minutes)
Duration
ISD5116
Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or
OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ
STATUS instruction that will give a status byte out the SDA line.
XCLK (External Clock Input)
This is the external clock input. To use internal clock, this pin must be grounded (suggest connecting
to V
selected for its internal oscillator by the Sample Rate Select bits. For precision timing control, external
clock signal can be applied through this pin. In the external clock mode, the device can be clocked
through the XCLK pin at 4.096 MHz as described in
Because the anti-aliasing and smoothing filters track the Sample Rate Select bits, one must, for
optimum performance, maintain the external clock at 4.096 MHz AND set the Sample Rate
Configuration bits to one of the four values to properly set the filters to the correct cutoff frequency as
described in
immediately divided by two internally.
INT (Interrupt)
INT is an open drain output pin. The ISD5100 Series interrupt pin goes LOW and stays LOW when an
8.73
10.9
13.1
17.5
SSD
). While in internal clock mode, the ISD5100 Series are operated at one of four internal rates
(Minutes)
Duration
ISD5108
section 7.4.3
4.36
5.45
6.55
8.75
RAC Waveform During Digital Erase @ 8kHz Operation
(Minutes)
Duration
ISD5104
on page 32. The duty cycle on the input clock is not critical, as the clock is
2.18
2.72
3.27
4.37
External Clock Input Table
(Minutes)
Duration
ISD5102
1.08
1.35
1.63
2.18
1.25 ms
- 49 -
TRACE
section 7.4.3
Sample
(kHz)
Rate
8.0
6.4
5.3
4.0
Required
on page 32.
Publication Release Date: Oct 31, 2008
Clock
(kHz)
4096
4096
4096
4096
ISD5100 SERIES
.25 ms
T
RACEL
FLD1
0
0
1
1
FLD0
0
1
0
1
Revision 1.42
Filter
Knee
(kHz)
3.4
2.7
2.3
1.7