ISD-ES511 Nuvoton Technology Corporation of America, ISD-ES511 Datasheet - Page 39

• Manufacturer Part Number: ISD-ES511
• Description: EVALUATION SYSTEM FOR ISD5100
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ChipCorder®r

Specifications of ISD-ES511

• Main Purpose: Audio, Voice Record/Playback
• Utilized Ic / Part: ISD5102, ISD5104, ISD5108, ISD5116
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

WaitACK
WaitSCLHigh
SendByte(0x40)
WaitACK
WaitSCLHigh
I2Cstop
Notes
1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low Address
2. I
3. Host processor must count RAC cycles to determine where the chip is in the erase process,
4. When the erase of the last desired row begins, the following STOP command (Command Byte
Byte will be ignored.
execute the STOP command that causes the end of the Erase operation.
one row per RAC cycle. RAC pulses LOW for 0.25 millisecond at the end of each erased
row. The erase of the "next" row begins with the rising edge of RAC. See the
RAC
= 80 hex) must be issued. This command must be completely given, including receiving the
ACK from the Slave before the RAC pin goes HIGH at the end of the row.
2
C bus is released while erase proceeds. Other devices may use the bus until it is time to
timing diagram on page 51.
- Exit Digital Mode Command
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Publication Release Date: Oct 31, 2008
ISD5100 SERIES
Digital Erase
Revision 1.42