STEVAL-ISB009V1 STMicroelectronics, STEVAL-ISB009V1 Datasheet - Page 12

• Manufacturer Part Number: STEVAL-ISB009V1
• Description: BOARD EVAL BATT MONITOR STC3100
• Manufacturer: STMicroelectronics
• Type: Battery Managementr

Specifications of STEVAL-ISB009V1

• Main Purpose: Power Management, Battery Monitor
• Embedded: No
• Utilized Ic / Part: STC3100
• Primary Attributes: Monitors Current, Voltage, Temperature
• Secondary Attributes: Includes Coulomb Counter for Charge/Discharge Status
• Board Size: 23 mm x 18 mm
• Interface Type: I2C
• Product: Power Management Modules
• Dimensions: 23 mm x 18 mm
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• For Use With/related Products: STC3100
• Other names: 497-10045

I2C interface
8
8.1
Table 6.
Table 7.
Table 8.
12/21
RegADDR7
DATA7
b7
b7
b7
1
I2C interface
Read and write operations
The interface is used to control and read the current accumulator and registers. It is
compatible with the Philips I2C registered trademark (version 2.1). It is a slave serial
interface with a serial data line (SDA) and a serial clock line (SCL).
●
●
A filter rejects the potential spikes on the bus data line to preserve data integrity.
The bidirectional data line supports transfers up to 400 kbit/s (fast mode). The data is shifted
to and from the chip on the SDA line, MSB first.
The first bit must be high (START) followed by the device address and read/write bit control.
Bits DevADDR0 to DevADDR2 are factory-programmable, the default device address value
being 70h (AddrID0 = AddrID1 = AddrID2 = 0). The STC3100 then sends an acknowledge
at the end of an 8-bit long sequence. The next 8 bits correspond to the register address
followed by another acknowledge.
The data field is the last 8-bit long sequence sent, followed by a last acknowledge.
Device address format
Register address format
Register data format
RegADDR6
DATA6
SCL: input clock used to shift data.
SDA: input/output bidirectional data transfers.
b6
b6
b6
1
RegADDR5
DATA5
b5
b5
b5
1
RegADDR4
DATA4
b4
b4
b4
0
DevADDR2
RegADDR3
DATA3
b3
b3
b3
DevADDR1
RegADDR2
DATA2
b2
b2
b2
DevADDR0
RegADDR1
DATA1
b1
b1
b1
RegADDR0
STC3100
DATA0
R/W
b0
b0
b0