V2DIP1-32 FTDI, Future Technology Devices International Ltd, V2DIP1-32 Datasheet - Page 20

• Manufacturer Part Number: V2DIP1-32
• Description: MOD MCU-USB HOST CTLR 24-DIP
• Manufacturer: FTDI, Future Technology Devices International Ltd
• Series: Vinculum-IIr

Specifications of V2DIP1-32

• Main Purpose: Interface, USB 2.0 Host/Controller
• Embedded: Yes, ASIC
• Utilized Ic / Part: VNC2-32Q
• Primary Attributes: Single A-Type Connector, UART / Parallel FIFO / SPI Interfaces
• Secondary Attributes: Second USB Port is Available via Pins, Traffic LEDs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 768-1058

Document Reference No.: FT_000163
V2DIP1-32 VNC2-32Q Development Module Datasheet Version 1.01
Clearance No.: FTDI# 150
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Appendix B – List of Figures and Tables
List of Figures
Figure 1.1 - V2DIP1-32 ................................................................................................................. 1
Figure 3.1 - V2DIP1-32 Module Pin Out (Top View) .......................................................................... 4
Figure 3.2 - V2DIP1-32 Module Pin Out (Bottom View) ..................................................................... 5
Figure 3.3 – Asynchronous FIFO Mode Read and Write Cycle. ........................................................... 11
Figure 5.1 Additional USB Port Configuration .................................................................................. 14
Figure 6.1 - V2DIP1-32 Dimensions (Top View) .............................................................................. 15
Figure 6.2 - V2DIP1-32 Dimensions (Side View) ............................................................................. 15
Figure 7.1 - V2DIP1-32 Schematic ................................................................................................ 16
List of Tables
Table 3.1 - Pin Signal Descriptions .................................................................................................. 6
Table 3.2 - Default Interface I/O Pin Configuration ........................................................................... 7
Table 3.3 - Data and Control Bus Signal Mode Options – UART ........................................................... 8
Table 3.4 - Data and Control Bus Signal Mode Options – SPI Slave ..................................................... 9
Table 3.5 - Data and Control Bus Signal Mode Options – SPI Master ................................................... 9
Table 3.6 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface ................................. 10
Table 3.7 - Asynchronous FIFO Mode Read Cycle Timing .................................................................. 11
Table 3.8 - Signal Name and Description – Debugger Interface ........................................................ 12
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