QF1DA512-DK Quickfilter Technologies LLC, QF1DA512-DK Datasheet - Page 41

• Manufacturer Part Number: QF1DA512-DK
• Description: KIT DEV FOR QF1DA512
• Manufacturer: Quickfilter Technologies LLC
• Series: SavFIRe™r

Specifications of QF1DA512-DK

• Main Purpose: Filters, Digital Filter Design
• Embedded: Yes, ASIC
• Utilized Ic / Part: QF1Da512
• Primary Attributes: 1 512 Tap FIR Filter, 12 ~ 24 Bit
• Secondary Attributes: Quickfilter Software Design Tool GUI, Works from 10 ~ 500ksps ADC Data Rates
• For Use With: WM2582 - EVALDI EARBUDS TYPE Y686-1006 - BOARD MSP-MOJO + EXPANSION HEADR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 686-1010

PRELIMINARY DATA SHEET
QF1Da512
List of Figures
Figure 1: 16 Pin QFN Package Pin out ................................................................................................................................... 9
Figure 2: Functional Block Diagram ...................................................................................................................................... 10
Figure 3: Configuration Data Timing ..................................................................................................................................... 12
Figure 4: Configuration Interface Transfer Format................................................................................................................ 13
Figure 5: Interface Modes ..................................................................................................................................................... 14
Figure 6: Data Format Selection ........................................................................................................................................... 14
Figure 7: Data Interface Timing Diagram .............................................................................................................................. 15
Figure 8: Data Interface Transfer Format ............................................................................................................................. 15
Figure 9: Data Header Masking Example ............................................................................................................................. 16
Figure 10: Averaging /Down-sampler Block Diagram ........................................................................................................... 17
Figure 11: I2S Mode .............................................................................................................................................................. 31
Figure 12: SPI Coprocessor Mode ........................................................................................................................................ 31
Figure 13: Inline Normal SPI Mode ....................................................................................................................................... 32
Figure 14: Inline Continuos SPI Mode .................................................................................................................................. 32
Figure 15: Inline Synchronous Serial Mode .......................................................................................................................... 33
Figure 16: Inline SPI DAC ..................................................................................................................................................... 33
Figure 17: ADC Configuration Read / Write .......................................................................................................................... 34
Figure 18: QF1Da512 Configuration, only SPI supported .................................................................................................... 34
Figure 19: I2C Master/Slave Interaction ............................................................................................................................... 35
Figure 20: I2C Master/Slave Command/Response Timing .................................................................................................. 36
Figure 21: I2C to SPI Bridge Circuit ...................................................................................................................................... 36
Figure 22: I2C Addressing Protocol ...................................................................................................................................... 37
Figure 23: VQFN 16, Bottom View ........................................................................................................................................ 38
Figure 24: VQFN 16, Top/Side View ..................................................................................................................................... 38
The contents of this document are provided in connection with Quickfilter Technologies, Inc. products. Quickfilter makes no representations or warranties with respect to the
accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No
license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Quickfilter's Standard
Terms and Conditions of Sale, Quickfilter assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to,
the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
Rev A8 January 7, 2009
41
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