QF1DA512-DK Quickfilter Technologies LLC, QF1DA512-DK Datasheet - Page 10

• Manufacturer Part Number: QF1DA512-DK
• Description: KIT DEV FOR QF1DA512
• Manufacturer: Quickfilter Technologies LLC
• Series: SavFIRe™r

Specifications of QF1DA512-DK

• Main Purpose: Filters, Digital Filter Design
• Embedded: Yes, ASIC
• Utilized Ic / Part: QF1Da512
• Primary Attributes: 1 512 Tap FIR Filter, 12 ~ 24 Bit
• Secondary Attributes: Quickfilter Software Design Tool GUI, Works from 10 ~ 500ksps ADC Data Rates
• For Use With: WM2582 - EVALDI EARBUDS TYPE Y686-1006 - BOARD MSP-MOJO + EXPANSION HEADR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 686-1010

3
Data Format and Control
The Data Format and Control block accepts the digital serial data. It separates any header information and checks for data valid and
then separates the data bits for processing. It also converts the data into the required format for the FIR filter. The data interface
supports the standard I2S and SPI bus protocols. The data interface consists of the dSCK, dCS, dSDI, and dSDO pins and allows for
digital data received on dSDI to be filtered or passed through to dSDO.
filtered data.
Averaging and Down-sampler
The Averaging / Down-sampler block down-samples the incoming data by a factor of 2 to 256. It also can be configured to average the
down sampled data. Default is bypassed. This block also supports a special I2S feature of channel duplication which converts the
standard left/right channel format to either all left or all right.
Finite Impulse Response Filter (FIR)
The FIR filter consists of up to 512 taps for a symmetric filter or 256 taps for an asymmetric filter.
Digital Gain and Compression (DGC)
DGC is used to maintain unity gain through the QF1Da512 for complex filters like those used in audio equalization. DGC is performed
sample by sample with an instant attack and release. Both Gain and Compression (ratio) are comprised of 4 integer bits and 12
fractional bits. Quickfilter Pro™ can automatically determine Gain and Compression settings. Direct access and guidance is also
available for advanced users.
Configuration Interface
The configuration interface supports the standard SPI bus protocol and operates in SLAVE mode. cSCK is capable of operating up to
20 MHz, although it may be run at much lower speeds.
The configuration interface consists of the cSCK, cCSn, cSDI and cSDO pins and is used to read and write the control registers and
program the coefficient memory space.
Rev A8 January 7, 2009
GENERAL DESCRIPTION
VDD33
dSDO
dSCK
dSDI
GND
dCS
15
16
6
5
4
3
Clk Gen
VDD18
14
Control
Format
Data
and
VDD18
12
clk_sys
Figure 2: Functional Block Diagram
PRELIMINARY DATA SHEET
Compression
Averager
DDS /
Gain and
GND
Digital
10
VDD33
11
10
Data RAM
FIR Filter
512 Tap
Max
If a header is used, it is passed unaltered along with the
TST
13
Registers
CTRL
Coefficient
RAM
RSTn
2
C
o
n
g
u
a
o
n
f
i
r
t
i
7
8
9
1
cSCK
cSDI
cCSn
cSDO
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QF1Da512